Reset Operation - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

CHAPTER 3 CPU
3.5.2

Reset Operation

When the CPU wakes up from a reset, the CPU selects the read address of the mode
data and reset vector according to the mode pin settings, then performs a mode fetch.
The mode fetch is performed after the oscillation stabilization delay time has passed
when power is turned on to a product with power-on reset, or on wake-up from stop
mode by a reset. If reset occurs during a write to RAM, the contents of the RAM address
cannot be assured.
I Overview of reset operation
During reset
operation
Mode fetch
(reset operation)
Normal operation
(RUN state)
46
Figure 3.5-2 Reset operation flow diagram
Software reset
Watchdog reset
NO
External reset input
Power-on reset
selected?
YES
NO
Power-on
or stop mode?
YES
Main clock oscillation
stabilization delay reset
state
Wakes up from external
reset?
YES
Fetch mode data
Fetch reset vector
Fetch the instruction code from the address
indicated by the reset vector and begin execution.
Power-on reset
(optional)
Main clock oscillation
stabilization delay reset
state
NO