Resets - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

3.5

Resets

The MB89950/950A series supports the following four types of reset source:
• External reset
• Software reset
• Watchdog reset
• Power-on reset (optional)
At reset, main clock oscillation stabilization delay time may or may not occur by the
operating mode and option settings.
I Reset source
Table 3.5-1 Reset source
Reset source
External reset
Software reset
Watchdog reset
Power-on reset
G
External reset
Inputting an "L" level to the external reset pin (RST) generates an external reset. Returning the reset pin to
the "H" level wakes up the CPU from the external reset.
When power is turned on to products with power-on reset or for external resets in stop mode, the reset
operation is performed after the oscillation stabilization delay time has passed and the CPU wakes up from
the external reset. External resets on products without power-on reset do not wait for the oscillation
stabilization delay time.
The external reset pin can also function as a reset output pin (optional).
G
Software reset
Writing "0" to the software reset bit in the standby control register (STBC: RST) generates a four-
instruction-cycle reset. The software reset does not wait for the oscillation stabilization delay time.
G
Watchdog reset
The watchdog reset generates a four-instruction-cycle reset if data is not written to the watchdog timer
control register (WDTC) within a fixed time after the watchdog timer starts. The watchdog reset does not
wait for the oscillation stabilization delay time.
Set the external reset pin to the "L" level.
Write "0" to the software reset bit in the standby control register (STBC: RST).
Watchdog timer overflow.
Power is turned on (only on products with a power-on reset).
Reset condition
CHAPTER 3 CPU
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