Interrupt Request Hold - NEC mPD780852 Series Preliminary User's Manual

19.4.5 Interrupt request hold

There are instructions where, even if an interrupt request is issued for them while another instruction is executed,
request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1 PSW.bit
• CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW.bit, $addr16
• BF PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
• EI
• DI
• Manipulate instructions for the IF0L, IF0H, IF1L, 1F1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, PR1H,
EGP, and EGN registers
Caution The BRK instruction is not one of the above-listed interrupt request hold instruction. However,
the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared
to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK
instruction, the interrupt request is not acknowledged. However, a non-maskable interrupt
request is acknowledged.
The timing with which interrupt requests are held pending is shown in Figure 19-15.
CPU processing
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-15. Interrupt Request Hold
Instruction N Instruction M
Preliminary User's Manual U14581EJ3V0UM00
Save PSW and PC, jump Interrupt servicing
to interrupt servicing program
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