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10.4 Watchdog Timer Operations
10.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to
detect any runaways.
A watchdog timer count clock (runaway detection time interval) can be selected by using bits 0 to 2 (WDCS0 to
WDCS2) of the watchdog timer clock select register (WDCS).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within
the set runaway time interval. The watchdog timer can be cleared and counting is started.
If RUN is not set to 1 and the runaway detection time is past, system reset or a non-maskable interrupt request
is generated according to the WDTM bit 3 (WDTM3) value.
The watchdog timer is cleared if RUN is set to 1.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Caution
The actual runaway detection time may be shorter than the set time by a maximum of 2
WDCS2
0
0
0
0
1
1
1
1
Remarks 1. f
: Main system clock oscillation frequency
X
2. Figures in parentheses apply to operation with f
CHAPTER 10 WATCHDOG TIMER
Table 10-4. Watchdog Timer Runaway Detection Time
WDCS1
WDCS0
12
0
0
f
/2
X
13
0
1
f
/2
X
14
1
0
f
/2
X
15
1
1
f
/2
X
16
0
0
f
/2
X
17
0
1
f
/2
X
18
1
0
f
/2
X
20
1
1
f
/2
X
Preliminary User's Manual U14581EJ3V0UM00
Runaway Detection Time
(489 µ s)
(978 µ s)
(1.96 ms)
(3.91 ms)
(7.82 ms)
(15.6 ms)
(31.3 ms)
(125 ms)
= 8.38 MHz.
X
8
/f
[sec].
X
147
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