Masked Interrupt Status Register; Table 23-27. Mis Register; Table 23-28. Mis Register Definitions - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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Analog-to-Digital Converter/Brownout Detector

23.3.2.14 Masked Interrupt Status Register

MIS is the Masked Interrupt Status Register. This Read Only register gives the masked
value of each interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
23-24

Table 23-27. MIS Register

31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R

Table 23-28. MIS Register Definitions

BIT
NAME
31:5
///
4
BROWNOUT
3
PENSYNC
2
EOSINTR
1
FWATERINTR
0
FOVRNINTR
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
22
///
0
0
0
0
R
R
R
R
10
9
8
7
///
0
0
0
0
R
R
R
R
0xFFFC3000 + 0xAC
DESCRIPTION
Reserved Read as zero.
Brown-Out Interrupt Status
0 = Brown-out Interrupt is not active.
1 = Brown-out Interrupt is active.
Pen Interrupt Status
0 = Pen Interrupt is not active.
1 = Pen Interrupt is active.
End-of-Sequence Interrupt Active
0 = EOCIA Interrupt is not active.
1 = EOCIA Interrupt is active.
FIFO Watermark Interrupt Active
0 = FIFO Watermark Interrupt is not active.
1 = FIFO Watermark Interrupt is active.
FIFO Overrun Interrupt Active
0 = FIFO Overrun Interrupt is not active.
1 = FIFO Overrun Interrupt is active.
6/25/03
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
0
0
0
0
0
R
R
R
R
R
17
16
0
0
R
R
1
0
0
0
R
R

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