Ssp Register Definitions; Control Register 0; Table 18-3. Ctrl0 Register; Table 18-4. Ctrl0 Register Definitions - Sharp Blue Treak LH75400 User Manual

Synchronous Serial Port

18.5.2 SSP Register Definitions

18.5.2.1 Control Register 0

CTRL0 is Control Register 0. CTRL0 contains five bit fields that control various SSP
functions. The active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:16
15:8
7
6
5:4
3:0
18-12

Table 18-3. CTRL0 Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
SCR
0 0 0 0 0
RW RW RW RW RW

Table 18-4. CTRL0 Register Definitions

Reserved Writing to these bits has no effect. Reading returns 0.
///
Serial Clock Rate The SCR value is used to generate the transmit and receive
SCR
bit rate of the SSP.
SPH SSPCLK Phase Applicable to Motorola SPI frame format only.
SPO SSPCLK Polarity Applicable to Motorola SPI frame format only.
Frame Format
00 = Motorola SPI frame format
FRF
01 = TI synchronous serial frame format
10 = National Microwire frame format
11 = Reserved, undefined operation
Data Size Select
0000 = Reserved, undefined operation
0001 = Reserved, undefined operation
0010 = Reserved, undefined operation
0011 = 4-bit data
0100 = 5-bit data
0101 = 6-bit data
0110 = 7-bit data
DSS
0111 = 8-bit data
1000 = 9-bit data
1001 = 10-bit data
1010 = 11-bit data
1011 = 12-bit data
1100 = 13-bit data
1101 = 14-bit data
1110 = 15-bit data
1111 = 16 bit data
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
SPH SPO
0 0 0 0
RW RW RW RW RW
0xFFFC6000 + 0x000
DESCRIPTION
6/17/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
FRF DSS
0 0 0 0 0
RW RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW