Address/Control Character Register0; Table 20-29. Actrl0 Register; Table 20-30. Actrl0 Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.10 Address/Control Character Register0

Register Bank: 0
The ACTRL0 Register contains a byte that is compared to each received character. The
exact function depends on the configuration of the IMD Register (see Section 20.3.2.23).
In Normal Mode, this register can be used to program a special control character; in this
case, a matched character is reported in the RST Register (see Section 20.3.2.17).
The maximum length of the control characters is eight bits. If the length is less than eight
bits, the character must be right-justified, with the leading bits filled with zeros. In µLAN
Mode, this register contains the 8-bit station address for recognition. In this mode, only
incoming address characters (that is, characters with the address bit set) are compared to
these registers. The PCRF bit in the RST Register is not set when an Address or Control
Character match occurs.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0

Table 20-29. ACTRL0 Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 20-30. ACTRL0 Register Definitions

NAME
/// Reserved Do not modify. Read as zero.
Data Bit [7] holds the most-significant bit. Bit [0] holds the least-
D7:D0
significant bit.
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
D7 D6
0 0 0 0 0
R R R RW RW
0xFFFC2000 + 0x1C
DESCRIPTION
6/17/03
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
D5 D4 D3 D2 D1
0 0 0 0 0
RW RW RW RW RW
UART2
16
0
R
0
D0
0
RW
20-21