Control Register; Table 12-4. Ctrl Register; Table 12-5. Ctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

12.3.2.4 Control Register

The Control Register reads and writes the configuration of the DMA Controller. The active
bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:14
13
12
11
10
9
8:7
6:5
31 30 29 28
0 0 0 0
RW RW RW RW RW
15 14 13 12
/// Dir ///
0 0 0 0
RW RW RW RW RW

Table 12-5. CTRL Register Definitions

NAME
/// Read as zero. Always write 0 to these bits.
0 = Peripheral is the source
Dir
1 = Peripheral is the destination
/// Reads as zero. Always write 0 to this bit.
Stream 3 Memory Transfer Selects memory-to-memory transfer for Stream3. Ig-
nored for data streams[2:0].
0 = Stream3 is not configured for memory-to-memory transfer.
Mem2Mem
1 = Stream3 is configured for memory-to-memory transfer. The DMA Controller disre-
gards any request from UART0TX and transfers data from source to destination as
fast as possible until MaxCnt expires.
/// Reads as zero. Always write 0 to this bit.
Current Source/Destination Loading Determines whether the Current Source Ad-
dress Register and the Current Destination Address Register load from the Source
Base registers and the Destination Base registers, respectively, when the DMA con-
troller is enabled.
AddrMode
0 = Wrapping Address Mode for source and destination. Registers load from their re-
spective Base Address registers when the DMA controller is enabled. (Default)
1 = Incremental Address Mode for source and destination. Registers are not reloaded
from their respective Base Address registers when the DMA controller is enabled.
DMA-to-Destination Data Width See Table 12-6. If you use a DeSize of '01', set the
DeSize
SoBurst value to '01'.
Peripheral Burst Size Defines the number of words in the peripheral burst. When the
peripheral is the source, these are the number of source-to-DMA words read into the
FIFO before writing FIFO contents to destination. When the peripheral is the destina-
tion, the DMA interface automatically reads the correct number of source words to
SoBurst
compile a SoBurst of DeWidth data. When stream 3 is configured as a memory-to-
memory transfer, SoBurst relates to the source side burst length. Table 12-7 shows
valid values. For memory-to-peripheral operations, if bits [6:5] = '00', bits [4:3] must =
'00'. If bits [6:5] = '01', bits [4:3] must = '01'.

Table 12-4. CTRL Register

27 26 25 24 23
///
0 0 0 0 0
RW RW RW RW
11 10 9 8 7
/// DeSize
0 0 0 0 0
RW RW RW RW
0xFFFE1000 + 0x14
FUNCTION
7/15/03
Direct Memory Access Controller
22 21 20 19
0 0 0 0
RW RW RW RW RW
6 5 4 3
SoBurst SoSize
0 0 0 0
RW RW RW RW RW
18 17 16
0 0 0
RW RW
2 1 0
0 0 0
RW RW
12-9