Gate Array Pin Descriptions (Ssc2571F0A) - Casio SF-7900E Service Manual & Parts List

Gate array pin descriptions (SSC2571F0A): Used in SF-7900E
Pin No. Name
1 VSS1
2 OSO
3 OSI
4 VL1
5~10 A0~3,A14,15
11 FE
12 CS1
13 CS2
14 CS3
15 OEI
16 VSS(GND)
17 VH1(VCC)
18 TXI
19 WEI
20 GC
21 IO0
22 DT
23 IO1
24 VIN
25 IO2
26 KON
27 IO3
28 VOB
29 IO4
30 INT
31 VH2(VCC)
32 VL2(VLL)
33 VSS(GND)
34 BBC
35 PDN
36 IO5
37 RLD
38 RA15
39 IO6
40 RA16
41 IO7
42 RA17
43 RA18
44 MS3
45 RA19
46 RA20
47 R15
48 VSS(GND)
49 VH3(VCC)
50 VDD1(VLL)
51 R16
52 R17
53 MSO
54 MS4
55 MS1
56 MS5
In/Out Description
In GND terminal
Out Clock out
In Clock in
In 6V input
In Address input
In Chip select signal from CPU
In Chip select signal from CPU
In Chip select signal from CPU
In Chip select signal from CPU
In Output enable signal from CPU
In GND terminal
In 9V input
In Transmission data input from CPU
In Write enable signal from CPU
In GC signal from CPU
In/Out Data bus line
In DT signal input
In/Out Data bus line
In Power ON signal from CPU (V2ON)
In/Out Data bus line
Out Switch control signal
In/Out Data bus line
Out Inverted signal for VIN
In/Out Data bus line
Out Interrupt signal
In 9V input
In 6V input
In GND terminal
Out Not used
In Power down detection input
In/Out Data bus line
Out Not used
Out Address bus output
In/Out Data bus line
Out Inverted signal for VIN
In/Out Data bus line
Out Address bus output
Out Address bus output
Out Not used
Out Not used
Out Not used
Out Address bus
In GND terminal
In 9V input
In 6V input
Out Address bus
Out Address bus
Out Chip enable signal for ROM
Out Chip select signal for RAM (Not used)
Out Not used
Out Not used
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