Casio SF-7900E Service Manual & Parts List page 11

CIRCUIT EXPLANATIONS
System chart
The circuitry operates in the following order:
1
VDD
11
Power supply
circuit
V1~V5
for LCD
VDD
VDD1
GND
KAC KIO
(Pin54)
(Pin53)
"L"
6
7
1. Supply 5V to VDD1 and VDD2.
2. Output "L" from SWO terminal.
3. Output "L" from IC4 and Q5 terminal.
4. Main switch ON.
5. Input "L" to SW terminal.
6. Input "L" from KAC terminal.
7. Push power on button switch.
8. CPU oscillation is generated.
9. Output "H" from V2ON terminal.
10. Output "L" from VOB terminal.
Low battery
detector
IC4
"H"
2 MHz
8
9
(Pin41)
(Pin45) (Pin40)
V2ON OSCI OSCO
(Pin70)
INT0
CPU
MAIN SWITCH
SW
(Pin36)
HD62076C03
5
"H"
ADDRESS BUS
DATA BUS
— 9 —
VDD
VSS
Gate array
VOB
(Pin24)
VIN
MSO
PDN OEO
SWO
(Pin62)
(Pin35) (Pin58)
2 12
3
"L"
"L" "L"
VDD
OFF
ON
4
(Pin24)
"L"
OE
14
ADDRESS
DATA
15
11. Output all LCD drive voltages.
12. Gate array sends ROM output enable
signal to OE terminal.
13. Gate array sends ROM Chip enable
signal to CE terminal.
14. CPU sends address to ROM.
15. CPU receives data from ROM.
10
(Pin28)
(Pin49)
13
"L"
(Pin22)
CE GND
ROM
(Operation program)