Gate Array Pin Descriptions (Μpd65005Gc-566-3B6); Power Supply Chip Ic Pin Descriptions (Sc371015Fu) - Casio SF-8500 Service Manual & Parts List

10-4. Gate array pin descriptions (µPD65005GC-566-3B6)
Pin No. Name
1~6, 8, 9 OI7~OI0
7, 33 GND
10 B15
11~13 A15,A01,A00
14 N.C.
15 DT
16~23 IO0~IO7
24 CSB
25 MON
26 LSI
27 LSO
28 PDN
29 BLI
30 DEB
31 VIN
32 VOT
34 VDD
35 OEI
36 WEI
37 BBC
38 CDE
39 VOB
40 SWO
41 BCN
42 MDP
43 OEO
44 WEO
45, 51 A19, A16
46, 47 R15, R16
48 EOB
49 RS0
50 CS3
52 RS3

10-5. Power supply chip IC pin descriptions (SC371015FU)

Pin No. Name
32, 22 GND1, 2
1, 19 VDD1, 2
2 Vo1
31 PDB
In/Out Status Status
of OFF of ON
In/Out L L
In L L
In L Pulse
In L Pulse
- - -
In H Pulse
In/Out L Pulse
In H Pulse
Out L L
In L L
Out H H
In H H
In H H
Out H Pulse
In L H
Out L H
In H H
In H Pulse
In H Pulse
Out L Pulse
In L H
Out H L
Out L L
In H H
In H L
Out L Pulse
Out L Pulse
In L Pulse
Out L Pulse
In H Pulse
Out H Pulse
In H Pulse
Out H Pulse
In/Out Status Status
of OFF of ON
In L L
In H H
Out H H
In L H
Description
Not used
GND terminal
Address input
Address input
Not used
GC signal input
Data bus line
Chip select signal from CPU
Not used
Connected to GND
Always "H"
Power down detection input
Battery detection V comp1 input
Chip selection signal for ROM (Charactor generator)
Power on signal input
Power on signal output
VDD terminal
Read signal input
Write signal input
Memory back-up battery scanning signal
IC card detection signal input
ROM power switching signal (Operation program)
Main switch control signal
BCON signal from CPU
MDP2 signal from CPU
Read signal for ROM
Not used
Address input
Address output
Chip enable signal from CPU
Chip enable signal for ROM (µPD27C4001EBGW-304)
Chip select signal from CPU
Chip enable signal for ROM (Character generator)
Description
GND terminal
Main battery positive terminal (+5V)
VDD output terminal (4.5V)
Power on switch signal from gate array
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