Cpu Pin Description (Hd62076C02) - Casio SF-8500 Service Manual & Parts List

10-3. CPU pin description (HD62076C02)

Pin No. Name
1~14,16,17 A0~A15
15,39, 100 VSS
24 WE
25 OE
26 FE
27 CS1
28 CS2
29 CS3
30 E0
31 E1
32 E2
33 E3
34 BCON
35 MDP2
36 SW
37 ONMK
38 TEST
40,41 OSC O/I
42 VOSC
43, 91 VDD1
44 VDD2
45 V2ON
46~53 KI7~KI0
54 KAC
55~65,67 KC0~KC11
66 GND
68 INT2
69 INT1
70 INT0
71 BRK
72 P0
73 P1
74 P2
75 P3
76 P4
77 P5
78 P6
79 P7
80 H1
81 WENL
82 H2
83 L1
84 L2
85 DT
86 PRO
87 FR
88 LP
89 GC
90 DE
92~99 IO7~IO0
18~23 RA14~19
In/Out Status Status
of OFF of ON
Out L Pulse
In GND GND
Out H Pulse
Out H Pulse
Out H Pulse
Out H H
Out H H
Out H Pulse
Out L Pulse
Out L H
Out L H
Out L H
Out H H
Out H L
In L L
In H H
In L L
In L Pulse
In L H
In H H
In H H
Out L H
In H H
Out L Pulse
Out H Pulse
In L L
In H H
In L H
In H H
In H H
Out H H
In L H
In H H
In L H
Out H Pulse
Out H Pulse
In H H
In H H
Out H H
In L L
Out H H
Out L H
Out L L
Out H Pulse
Out L H
Out L Pulse
Out H Pulse
Out H Pulse
Out H Pulse
In/Out L Pulse
Out L Pulse
Description
Address Bus line
GND terminal
Write signal
Read signal
Not used
Not used
Chip select signal for gate array
Chip select signal for ROM (Charactor generator)
Chip enable signal for ROM (Operation program)
Chip enable signal (Not used)
Chip enable signal (Not used)
Chip enable signal (Not used)
BCN signal to gate array
MDP signal to gate array
Switch signal (When switches are at ON position)
Battery detection V comp1 input
TEST terminal (connect to GND)
Clock input
Power input for Clock
VDD input terminal
VDD input terminal
Power on output signal
Key input signal (K17...Not used)
Power on switch signal output
Key common signal output
GND terminal
Interrupt signal from ROM (Charactor generator)
Interrupt signal for transmission
Interrupt signal for transmission
VDD input terminal
Transmission data output
Reception data input
Card lock switch input
IC card detection signal input
KC 12 key common signal output
KC 13 key common signal output
Memory back-up battery detection input
Battery detection V comp2 input
Display contrast control signal output (Up/Down)
GND terminal
Not used
Chip enable signal for gate array
Dispray contrast control clock signal
Not used
LCD driver mode selection signal
LCD driver synchronous signal
LCD driver latch pulse signal
GC signal output
LCD driver data latch clock signal
Data bus line
Address line (Used exept RA 14)
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