Sharp ER-A770 Manual page 50

3-2. 0page area
The 0page area consists of four spaces: the ROM mapped area,
internal and external I/O areas.
The ROM mapped space have been devised for the following pur-
poses:
Simplifying the procedure for booting the IPL program
Achieving high-speed accessing, and accessing by abbreviated
instructions.
000000h
ROM mapping area
00FE80h
Internal I/O area
00FF80h
External I/O area
00FFFFh
Fig. 3
3-4. ROM space
Fig.5 shows the ROM space. The ER-A770 uses 2MB of NOR-type
flash memory instead of conventional ROM, so that the FROS1# from
the MPCA8 is input into the chip enable of the flash memory.
200000h
ROS1
(MAX4MB)
5FFFFF
Fig. 5
* The ROM area 200000h to
20FFFFh (ROS1 lower 64KB)
is mapped on the ROMmapping
area.
* The internal I/O area is used
for peripheral modules inside
the CPU; the external I/O area
is used for peripheral modules
outside the CPU.
For more information, refer to
the H8/510 hardware manual
and peripheral device
specification.
I/O area
* Lower 64KB of the ROS1 is
mapped on the 0 page area.
* ROS1 is decoded by
MPCA8.
3-3. I/O areas
The addresses from 00FF80h to 00FFFFh are called the internal I/O
area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
00FE80h
Internal I/O area
00FF80h
MPCCS
00FFA0h
Expanded MPC
(not used)
00FFB0h
MCR1Z
00FFB4h
MCR2Z
00FFB8h
T/PZ
00FFBCh
PRNZ (not used)
00FFC0h
OPCCS1
00FFD0h
OPCCS2
00FFE0h
CPCSZ (not used)
Not used
00FFF0h
TPRCI (not used)
00FFFFh
Fig. 4
3-5. VRAM & RAM space
The VRAM is the display memory of the LCD.
600000h
RAS1
(2MB)
800000h
A00000h
RAS2
(2MB)
BFFFFFh
VRAM
(1MB)
D00000h
Fig. 6
* MPCCS and expanded MPC
signals are base signals for
MPCA8 internal register
decode. There is no external
signal.
* MCR1Z and MCR2Z are chip
select signals for the magnet
card reader.
(Use lower 2bytes.)
* T/PZ is the internal decode
signal for USART built in
MPCA8. Thereis no external
signal. (Use lower 2bytes.)
* OPCCS1 and OPCCS2
signals are decoded inside
the OPC (OPTION PERIP-
HERAL CONTROLLER)
using the option decode
signal OPTCS. There is no
external signal.
OPTCSZ
* CPCSZ is CPC select for
Centronics Interface.
* All the decode signals in the
area in the figure are supported
by MPCA8.
* RAS1 signals from MPCA8
correspond to 2MB 600000h to
7FFFFFh.
* OPTION RAM board (1MB and
2MB) interfaces using RAS2
as the base signal.
* The actual VRAM is 512KB,
but it is accessed by every
128KB of bank according to
VGAC specification.