Motorola DSP56367 User Manual page 464

Description
RHCKD
HCKR is input
0
1 HCKR is output
Description
RFSD
0 FSR is input
1 FSR is output
Description
RCKD
External clock source used
0
Internal clock source
1
RHCKP
Clockout on rising edge of receive clock,
0
latch in on falling edge of receive clock
Clockout on falling edge of receive clock,
1
latch in on rising edge of receive clock
RFSP
0 Frame sync polarity positive
1
Frame sync polarity negative
RCKP
Clockout on rising edge of receive clock,
0
latch in on falling edge of receive clock
Clockout on falling edge of receive clock,
1
latch in on rising edge of receive clock
23 22 21 20 19 18
RHCKD RFSD RCKD RHCKP RFSP RCKP
RCCR - ESAI Receive Clock Control Register
X: $FFFFB8 Reset: $000000
Description
Description
Description
17 16 15 14 13 12 11
RFP3 RFP2 RFP1 RFP0 RDC4 RDC3 RDC2
RFP [3:0] Description
Sets divide rate for receiver high frequency clock
Range $0 - $F (1 -16). See 8.3.3.4
RDC [4:0] Description
Controls frame rate dividers
Range 00000 - 11111 (1-32) See 8.3.3.2
RPSR Description
0 Divide by 8 prescaler operational
1 Divide by 8 prescaler bypassed
RPM [7:0]
Specifies prescaler ratio for the
receive clock generator
Range from $00 - $FF (1 - 256).
See 8.3.3.1
10 9 8 7 6 5
RDC1 RDC0 RPSR RPM7 RPM6 RPM5 RPM4
ESAI
Description
4 3 2 1 0
RPM1 RPM0
RPM3 RPM2