Pll Initialization - Motorola DSP56367 User Manual

Core Configuration

PLL Initialization

6.6 PLL INITIALIZATION
6.6.1 PLL MULTIPLICATION FACTOR (MF0-MF11)
The DSP56367 PLL multiplication factor is set to 6 during hardware reset, i.e. the
Multiplication Factor Bits MF0-MF11 in the PLL Control Register (PCTL) are set to $005.
6.6.2 PLL PRE-DIVIDER FACTOR (PD0-PD3)
The DSP56367 PLL Pre-Divider factor is set to 1 during hardware reset, i.e. the Pre-Divider
Factor Bits PD0-PD3 in the PLL Control Register (PCTL) are set to $0.
6.6.3 CRYSTAL RANGE BIT (XTLR)
The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The
on-chip crystal oscillator is not used on the DSP56367 since no XTAL pin is available. The
XTLR bit is set to zero during hardware reset in the DSP56367.
6.6.4 XTAL DISABLE BIT (XTLD)
The XTAL Disable Bit (XTLD) is set to 1 (XTAL disabled) during hardware reset in the
DSP56367.
6.7 DEVICE IDENTIFICATION (ID) REGISTER
The Device Identification Register (IDR) is a 24 bit read only factory programmed register
used to identify the different DSP56300 core-based family members. This register specifies
the derivative number and revision number. This information may be used in testing or by
software. Table 6-8 shows the ID register configuration.
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