Serial Interface Channel 2 Block Diagram - NEC PD78052 User Manual

Receive Buffer
(RXB/SIO2)
Control Circuit
Receive Shift
RxD/SI2/
Register (RXS)
P70
TxD/SO2/
P71
PM71
Reception
PM72
ASCK/
SCK2/P72
Note See Figure 19-2 for the baud rate generator configuration.
CHAPTER 19 SERIAL INTERFACE CHANNEL 2
Figure 19-1. Serial Interface Channel 2 Block Diagram
Asynchronous
Serial Interface
Status Register
PE FE OVE
Register
Direction
Control
INTSR/INTCSI2
Circuit
ISRM
CSIM
CSIE2 CSCK
22
Serial Operating
Mode Register 2
Internal Bus
Asynchronous
Serial Interface
Mode Register
Direction
TXE RXE PS1 PS0 CL
Control Circuit
Transmit Shift
Register
(TXS/SIO2)
INTSER
Transmission
Control Circuit
Control
Circuit
INTST
Baud Rate Generator
CSIE2
TXE
RXE
MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0
Internal Bus
SL ISRM SCK
SCK Output
Note
f -f /2 10
xx xx
SCK
4 4
Baud Rate Generator
Control Register
441