Serial Interface Channel 0 Block Diagram - NEC PD78052 User Manual

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
Figure 17-2. Serial Interface Channel 0 Block Diagram
Serial Operating Mode Register 0
CSIE0 COI WUP
BSYE
Control
Circuit
SI0/SB0/
SDA0/P25
PM25
Output
Control
SO0/SB1/
SDA1/P26
PM26
Output
Control
CLD
SCK0/
SCL/P27
PM27
Output
Control
Remark Output Control selects between CMOS output and N-ch open drain output.
Internal Bus
CSIM CSIM CSIM CSIM CSIM
04 03 02 01 00
Selector
P25
Output Latch
Selector
P26 Output Latch
P27
Output Latch
Slave Address
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Register (SVA)
SVAM
Match
CLR SET
Serial I/O Shift
D Q
Register 0 (SIO0)
Stop Condition/
ACKD
Start Condition/
WUP
CMDD
Acknowledge
RELD
Detector
Serial Clock
Counter
Serial Clock 1/16
Selector
Divider
Control Circuit
CSIM00 CSIM00
CSIM01 CSIM01
CLD SIC SVAM
CLC WREL WAT1 WAT0
Interrupt Timing
Specify Register
Internal Bus
Serial Bus Interface
Control Register
Acknowledge
Output Circuit
Interrupt
Request
Signal
INTCSI0
Generator
TO2
Selector f /2-f /2 8
xx xx
4
2
TCL33 TCL32 TCL31 TCL30
Timer Clock
Select
Register 3
345