Slave Wait Release (Transmission) - NEC PD78052 User Manual

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
(2) Slave wait release (slave transmission)
Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or
execution of an serial I/O shift register 0 (SIO0) write instruction.
If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the
clock rises without the start transmission bit being output in the data line. Therefore, as shown in Figure 17-
25, data should be transmitted by manipulating the P27 output latch through the program. At this time,
control the low-level width ("a" in Figure 17-25) of the first serial clock at the timing used for setting the P27
output latch to 1 after execution of an SIO0 write instruction.
In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is
completed), set 1 in the WREL flag of SINT and release the wait.
For these timings, see Figure 17-23.
Master device operation
Software operation
Hardware operation
Transfer line
SCL
SDA0(SDA1)
Slave device operation
Software operation
Hardware operation
386
Figure 17-25. Slave Wait Release (Transmission)
Setting Setting
ACKD CSIIF0
9
A0 R ACK
ACK Setting
output
CSIIF0
Writing
FFH
to SIO0
a
1
D7
P27 P27
Write
output data output
latch 0 to SIO0 latch 1
Wait
release
Serial reception
2 3
D6 D5
Serial transmission