Sampling Clock Select Register Format - NEC PD78052 User Manual

(7) Sampling clock select registers (SCS)
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is removed with sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS value to 00H.
Symbol 7 6 5
0 0 0
SCS
N
Caution f /2 is the clock supplied to the CPU, and f
XX
peripheral hardware. f
Remarks 1. N
2. f
XX
3. f
X
4. MCS : Bit 0 of oscillation mode selection register (OSMS)
5. Figures in parentheses apply to operation with f
190
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-9. Sampling Clock Select Register Format
4 3 2 1 0
0 0 0 SCS1 SCS0
N
/2 is stopped in HALT mode.
XX
: Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)
(N = 0 to 4)
: Main system clock frequency (f
: Main system clock oscillation frequency
Address After Reset
FF47H 00H
INTP0 Sampling Clock Selection
SCS1 SCS0
MCS = 1
N
0 0 f /2
XX
7 7
0 1 f /2 f /2 (39.1 kHz)
XX X
5 5
1 0 f /2 f /2 (156.3 kHz)
XX X
6 6
1 1 f /2 f /2 (78.1 kHz)
XX X
5 6
/2 , f /2 , and f /2
XX XX XX
or f /2)
X X
= 5.0 MHz.
X
R/W
R/W
MCS = 0
8
f /2 (19.5 kHz)
X
6
f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
X
7
are clocks supplied to