Clock Setup Example - HP 81200 User Manual

Introduction to the System
32
Example:
If the desired clock rate is 100 MHz, the minimum blocklength granularity
is 4, which leads to 256 Kbit memory depth and a frequency multiplier
range of 1/4 ... 4. That means, an individual channel can run at 25 MHz,
50 MHz, 100 MHz, 200 MHz, or 400 MHz.
Other possible FMR factors for this clock rate are:
• 8, which leads to 512 Kbit memory depth, granularity 8, FMR 1/8 ... 2.
• 16, which leads to 1 Mbit memory depth, granularity 16, FMR 1/16 ... 1.
The relations are shown in the table below.
Table 1 Matrix of Block Length Granularity, Frequency Multiplier Range, Memory Depth
and System Clock Frequency
Block Length
Granularity
1 bit (=1)
2 bits (=2)
4 bits (=4)
8 bits (=8)
16 bits (=16)
a
For frequencies below 651.041666 kHz it is not possible to select fractions of the system
clock frequency for individual connectors. Therefore it is recommended to set the global
system clock frequency (or the global system period) to the lowest/longest frequency/period
required in your application and multiply by 2, 4, 8 or 16 at the individual connectors as re-
quired.
b
This is the range of multiples and fractions that can be used at individual connectors. If
you have most of your signals at 40 MHz and your pattern lengths are less then 64 Kbit, then
you can choose blocklength granularity 1. You have the chance to set individual connectors
to a multiple of this general setting. For example, selecting 16 as the multiply factor for a
connector gives you 1 Mbit memory depth and 640 MHz with a blocklength granularity of
16.
c
Subtract 32 x blocklength granularity, as this memory space is occupied by a 2
and the sequencing initialization.
d
Not available for dual analyzer frontends in the Compare and Acquire around Error and
Compare and Capture mode
e
Not available for dual generator and analyzer frontends.
f
For single-ended analyzer frontends not available in the Compare and Acquire around Er-
ror and Compare and Capture mode.

Clock Setup Example

Every channel can be set individually to multiples or fractions of 2 of the
chosen system clock frequency.
If, for example, most of your signals are at 200 MHz, then the
corresponding blocklength granularities you can choose from are either 8
or 16 (= block length resolution).
If you have chosen 8 as the general blocklength granularity, then each data
port and pulse port or each terminal of a pulse port can be set individually
to frequencies of 1/8, 1/4, 1/2, 1 or 2 times the system clock frequency.
HP 81200 Data Generator/Analyzer Platform User Guide, Revision 2.1
Frequency Multiplier
a,b
Range
1, 2, 4, 8, 16
1/2, 1, 2, 4, 8
1/4, 1/2, 1, 2, 4
d
1/8, 1/4, 1/2, 1, 2
e,f
1/16, 1/8, 1/4, 1/2, 1
Timing Principles
Memory
c
Depth System Clock Rates
 41.67 MHz
64 Kbit
 83.83 MHz
128 Kbit
 166.67 MHz
256 Kbit
 333.33 MHz
512 Kbit
 660 MHz
1 Mbit
5
-1 PRxS