Motorola MVME2401-1 Installation And Use Manual page 59

Table 3-6. PPC60x Originated Bandwidth Matrix
First 2
Cache Lines
Transaction
MBytes
Clks
64-bit Writes 14
64-bit Reads -
32-bit Writes 14
32-bit Reads -
64-bit Writes 14
64-bit Reads -
32-bit Writes 14
32-bit Reads -
64-bit Writes 14
64-bit Reads -
32-bit Writes 14
32-bit Reads -
64-bit Writes 14
64-bit Reads -
32-bit Writes 14
32-bit Reads -
64-bit Writes 14
64-bit Reads -
32-bit Writes 14
32-bit Reads -
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First 4
Cache Lines
MBytes
Clks
Sec Sec
381 58 184
- - -
381 78 137
- - -
457 38 337
- - -
457 50 256
- - -
457 67 191
- - -
457 98 131
- - -
305 48 178
- - -
305 64 133
- - -
305 29 294
- - -
305 37 231
- - -
First 6
Continuous
Cache Lines
MBytes Clks/
Clks
Sec Line
108 148 25
- - 32.5
148 108 35
- - 42.5
68 282 15
- - 22.5
92 209 21
- - 28.5
127 151 30
- - 36
182 105 42
- - 48
88 145 20
- - 28
120 107 28
- - 36
49 261 10
- - 18
65 197 14
- - 22
Block Diagram
Clock
Ratio
MBytes
Sec
107 5:2
82
76
63
213 3:2
142
152
112
107 3:1
89
76
67
107 2:1
76
76
59
213 1:1
118
152
97
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