And — Logical And - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
6.3.3 AND — LOGICAL AND
dst,src
AND
dst  dst AND src
Operation:
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. If the corresponding bits in two operands are both logic ones, AND operation results
in a "1" bit being stored in Z bit of FLAG; otherwise a "0" bit value is stored. The contents of the
source remain unaffected.
C: Unaffected.
Flags:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
opc
opc
opc
Given R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, and register 03H = 0AH:
Examples:
AND
AND
AND
AND
AND
In the first example, destination working register R1 contains the value 12H and source working
register R2 contains the value 03H. The statement "AND R1,R2" logically ANDs the source
operand value 03H with the destination operand value 12H, leaving the value 02H in register R1.
dst | src
src dst
dst src

R1,R2

R1,@R2

01H,02H

01H,@02H

01H,#25H
Bytes
2
3
3
R1 = 02H, R2 = 03H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
6-15
6 INSTRUCTION SET
Cycles Opcode
(Hex)
4 52
6 53
6 54
6 55
6 56
Addr Mode
dst src
r r
r lr
R R
R IR
R IM