System-Level Interrupt Control Registers - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

5.1.6 SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:

The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).

The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).
Control Register
Interrupt mask register
Interrupt priority register
Interrupt request
register
System mode register
NOTE: All interrupts must be disabled before IMR register is changed to any value. Using DI instruction is recommended.
Table 5-1 Interrupt Control Register Overview
ID R/W
IMR R/W Bit settings in the IMR register enable or disable the interrupt
processing for each of the eight interrupt levels (IRQ0–IRQ7).
IPR R/W Controls the relative processing priorities of the interrupt
levels. The eight levels of S3F84B8 are organized into three
groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is
IRQ2, IRQ3, and IRQ4, and group C is IRQ5, IRQ6, and
IRQ7.
IRQ R This register contains a request pending bit for each interrupt
level.
SYM R/W This register enables/disables fast interrupt processing and
dynamic global interrupt processing.
Function Description
5-5
5 INTERRUPT STRUCTURE