Write-Data Transfer - Motorola DSP56009 User Manual

Example 4-3 Successive Memory-Read Transfers with ERTS = 1 (Continued)
movep X:<<EDRR0,X0
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movep X:<<EDRR0,X0
4.5.3

Write-Data Transfer

Write transfers are triggered by writing data into the EMI Data Write Register
(EDWR). The word address for a write transfer is obtained by subtracting the
contents of the EWOR from the contents of the EBARx (the contents of EOR is of no
significance in a memory-write transfer). When new data is written into the EDWR,
the EDWE status bit is cleared (data register full). The data is then transferred to the
EDRB (if the EDRB is empty), setting EDWE. The EMI controller then performs a
number of memory write cycles. A data-word-write transfer can require one, two,
three, four, or six memory accesses, as specified by bits EWL[1:0] and EBW. The
nibbles or bytes written are read from the EDRB until the whole word is stored. If
EDWR is empty, the next data word to be written to memory can be stored in EDWR,
triggering a pending (pipelined) write operation. A pending-write operation will
proceed as soon as the EDRB is empty, permitting the transfer of the contents of
EDWR to the buffer. The DSP programmer can interrogate the EDWE status bit or,
optionally, the write interrupt can be generated when EDWE is set. Alternatively, the
DSP programmer can choose to write to EDWR after a minimum number of
instruction cycles such that EDWR can be guaranteed to be empty.
A memory-write transfer only starts when the EDRB is full (loaded with the data to
be stored to memory). Data is only transferred from EDWR to the EDRB if the buffer
is empty. This feature ensures synchronization between memory writes and DSP
writes, as long as the DSP ensures that writes to EDWR occur only if EDWR is empty.
MOTOROLA
; read the data triggered by
; the (n–3) EDRR read.
; perform other operations
; or poll EDRF for EDRR full
; or wait a sufficient number of Icyc
; and then,
; read the data triggered by
; the (n–2) EDRR read
DSP56009 User's Manual
External Memory Interface
EMI Operating Considerations
4-43