Table 4-12 Relative Addressing Extension Bits; Sram Absolute Addressing - Motorola DSP56009 User Manual

External Memory Interface
EMI Address Generation
When using the SRAM or DRAM Relative Addressing modes, the physical addresses
are generated by the Address Format Conversion circuit after appending extension
bits to the right of the word address. Table 4-12 shows the extension bits used for
every possible combination of word length and bus width, the number of accesses
required (equal to the number of physical addresses generated) and the states that
the extension bits run through during the accesses.

Table 4-12 Relative Addressing Extension Bits

Word Length
8
8
12
16
12 or 16
20
24
20 or 24
16 (24 Address)
16 (24 Address)
4.3.1

SRAM Absolute Addressing

The SRAM Absolute Addressing mode is selected when EAM[3:0] = 0000. In this
addressing mode, the physical address is formed by writing the 15 LSBs of the
calculated word address (A[14:0]) directly to the MA[14:0] address pins. The A[23:15]
portion of the word address is ignored. No extension bits are used in the physical
address generation. MA15 and MCS0 are held high.
If more than one physical address must be accessed to complete the word transfer,
EBARx must be post-incremented by one after each physical address access,
otherwise the same physical address will be accessed more than once. In this case, it
is required that the appropriate control bit be set in the ECSR (EINR for reads, EINW
for writes). The EMI will execute the series of accesses required, incrementing EBARx
after each access, packing (during a read operation) or unpacking (during a write
operation) the data word segment. The accesses proceed from the least significant to
the most significant portion of the word. For each of the accesses, the contents of
4-24
Bus No.
Width Access
4-bit 2
8-bit 1
4-bit 3
4-bit 4
8-bit 2
4-bit 5
4-bit 6 010, 011, 100, 101, 110, 111
8-bit 3
4-bit 4
8-bit 2
DSP56009 User's Manual
Running Order
0,1
none
01, 10, 11
00, 01, 10,11
0,1
011, 100, 101, 110, 111
01, 10, 11
100, 101, 110,111
10, 11
Active Extension
Bits
C0
none
C1, C0
C1, C0
C0
C2, C1, C0
C2, C1, C0
C1, C0
C2, C1, C0
C1, C0
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