Off Line" Refresh - Motorola DSP56009 User Manual

External Memory Interface
DRAM Refresh
4.4.3.2

"Off Line" Refresh

If the user application has a real-time loop, in which the program initiates external
data accesses after which the EMI channel is idle, it is possible to use this idle-time
window to refresh the DRAM in a burst manner. This method is useful for real-time
applications where data transfers should be performed at maximum speed and the
number of instruction cycles per data transfer is critical.
During initialization the user should set the ECSR EDTM bit and the applicable bits
in the ERCR for the appropriate DRAM Timing mode and refresh rate. During the
time window, when no external data accesses are executed, the user should set the
ERCR refresh Enable bit (EREF), turning it off before exiting the time window. When
the EREF bit is set, the refresh timer will initiate refresh cycles and this bit is cleared
once more. Care should be taken to ensure that a sufficient number of refresh cycles
are executed during the time EREF is set. Refer to Section 4.4.5 for more details.
4.4.3.2.1 OnCE Port Debug Mode Consideration
OnCE port operation does not affect the internal refresh timer. No special
consideration is necessary when using the "on line" refresh method. If using the "off
line" refresh method, however, the execution can stop when the refresh timer is off
and data stored in the DRAM can be lost. In order to avoid this situation, the user
should set the ERCR ERED bit, and refresh cycles will be initiated by the internal
refresh timer according to the ERCR setting only when the OnCE port is in the Debug
mode.
4.4.4 Software Controlled Refresh
If the user application has a real-time loop, where the program initiates external data
accesses after which the EMI channel is idle, it is possible to use this idle time
window to refresh the DRAM in a burst manner. This method is useful for real-time
applications where data transfers should be performed at maximum speed and the
number of instruction cycles-per-data-transfer is critical.
During initialization the user should set the ECSR EDTM bit (and the applicable bits
in the ERCR) to select the appropriate DRAM Timing mode and refresh rate. During
the time window, when no external data accesses are executed, the user should set
the ERCR one-shot refresh enable bit (EOSR), thus inserting one refresh cycle at a
time. Care should be taken to ensure that a sufficient number of refresh cycles are
executed. Refer to Section 4.4.5 for more details.
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