Table 18-3. Irqstatus Register; Table 18-4. Irqstatus Fields; Register Descriptions - Sharp LH79524 User Manual

Vectored Interrupt Controller

18.2.2 Register Descriptions

This section describes the bit fields, reset values, and uses of the registers. For simplicity,
all of the following register tables indicate the default base addresses.
18.2.2.1 IRQ Status Register (IRQSTATUS)
This Read Only register provides the status of all interrupts [31:0] after IRQ masking. Bits
[31:0] correspond to the interrupt number in Table 18-1.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:0 IRQStatus
18-6
Table 18-2. VIC Register Summary (Cont'd)
ADDRESS OFFSET
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x240 - 0x308
0x30C
0x310

Table 18-3. IRQSTATUS Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 18-4. IRQSTATUS Fields

NAME
Interrupt Status After Masking Shows the status of the interrupts after
masking by the INTENABLE and INTSELECT Registers.
For each bit:
1 = Interrupt is active and generates an IRQ exception to the ARM7 core
0 = Interrupt is not active
NAME
VECTCTRL8 Vector Control 8 Register
VECTCTRL9 Vector Control 9 Register
VECTCTR10 Vector Control 10 Register
VECTCTRL11 Vector Control 11 Register
VECTCTRL12 Vector Control 12 Register
VECTCTRL13 Vector Control 13 Register
VECTCTRL14 Vector Control 14 Register
VECTCTRL15 Vector Control 15 Register
/// Reserved — Do not access
ITOP Interrupt Test Output Register
/// Reserved — Do not access
26 25 24 23
IRQStatus
0 0 0 0
RO RO RO RO
10 9 8 7
IRQStatus
0 0 0 0
RO RO RO RO
0x000
0xFFFFF000 +
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
DESCRIPTION
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO