Ethernet MAC Controller
6.3.3.13 Receive Resource Errors (RXRERR)
This
register counting the number of frames that were address matched but could not be copied to
memory because no receive buffer was available.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:16
15:0
6.3.3.14 Receive Overrun Errors (RXOVERR)
Recieve overrun errors are tabulated in this register.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:8
7:0
6-44
Table 6-58. RXRERR Register
31
30
29
28
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
0
0
0
0
RW
RW
RW
RW
RW
NAME
///
Reserved Reading returns 0. Write the reset value.
Receive Resource Errors The number of frames that were address matched
RXRERR
but could not be copied to memory because no receive buffer was available.
Table 6-60. RXOVERR Register
31
30
29
28
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
///
0
0
0
0
RO
RO
RO
RO
RO
Table 6-61. RXOVERR Fields
NAME
///
Reserved Reading returns 0. Write the reset value.
Receive Overruns Number of frames that are address recognized but
RXOVERR
were not copied to memory due to a receive DMA overrun.
27
26
25
24
23
///
0
0
0
0
0
RO
RO
RO
RO
11
10
9
8
7
RXRERR
0
0
0
0
0
RW
RW
RW
RW
0xFFFC7000 + 0x6C
Table 6-59. RXRERR Fields
FUNCTION
27
26
25
24
23
///
0
0
0
0
0
RO
RO
RO
RO
11
10
9
8
7
0
0
0
0
0
RO
RO
RO
RW
0xFFFC7000 + 0x70
FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
RXOVERR
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW