Table 7-19. Dynmref Register; Table 7-20. Dynmref Fields; Dynamic Refresh Register (Dynmref) - Sharp LH79524 User Manual

External Memory Controller

7.5.2.5 Dynamic Refresh Register (DYNMREF)

This register configures dynamic memory operation.
This register should only be modified during system initialization, or when there are no
current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that changing
parameters will not corrupt external data. Low-Power Mode automatically refreshes
SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh (DYNMC-
TRL:SR = 1) prior to entering Disable. However, these control bits can, if necessary, be
altered during normal operation.
Writing a value of 0x000 disables refreshing. Programming any other value, 'n', results in
a delay between refresh cycles of 16 × n. For example, for the refresh period of 16 µs, and
an HCLK frequency of 50 MHz, the following value must be programmed into this register:
(16 × 10
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:11
10:0
7-34
÷
-6 6
× 50 × 10 ) 16 = 50, or 0x032

Table 7-19. DYNMREF Register

31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0
RO RO RO RO RO

Table 7-20. DYNMREF Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Refresh Timer (×16)
For REFRESH = 0x000: Refresh disabled
REFRESH
For REFRESH between 0x001 and 0xFFF:
HCLK cycles between SDRAM refresh cycles = 16 × (REFRESH)
26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0 0
RW RW RW RW
0xFFFF1000 + 0x024
FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
REFRESH
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW