Table 9-6. Icsar Register; Table 9-7. Icsar Fields - Sharp LH79524 User Manual

2
I C Module
BITS
3
2
1:0
9.2.2.2 I
Software programs this register with the unit address used by the I
Slave mode. In 7-bit addressing mode, the entire address is contained in this register. In
7-bit mode, bit 0 is not used.
In 10-bit addressing mode, this register holds the lower 8 address bits; the upper 2 address
bits and the R/W bit are in the ICUSAR register. This register is not used in Master mode.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS NAME
31:8
7:0
9-8
Table 9-5. ICCON Fields (Cont'd)
NAME
Fast/Standard Speed Use this bit to set the transaction speed of the I
SPEED
1 = Fast interface speed (400 kbit/s)
0 = Standard interface speed (100 kbit/s)
2
I C Enable This bit turns the I
I2CEN
2
1 = I C Module is enabled
2
0 = I C Module is disabled (SCL and SDA are not driven)
2
I C Module Mode The I
2
I C Module.
2
11 = I C Master Mode 10-Bit addressing
MODE
2
10 = I C Master Mode 7-Bit addressing
2
01 = I C Slave Mode 10-Bit addressing
2
00 = I C Slave Mode 7-Bit addressing
2
C Slave Address Register (ICSAR)
31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
///
0 0 0 0
RO RO RO RO RO
/// Reserved Reading returns 0. Write the reset value.
Least-Significant 7 bits of Slave Address SLAD7[7:1] holds the lower 7 bits
2
of the I C Module's Slave address. In 10-bit addressing mode, SLAD7[7:0] holds
SLAD7
the lower 8 bits of the slave address. In 7-bit mode, SLAD7[7:1] contains the ad-
dress, and SLAD7[0] is not used.
DESCRIPTION
2
C Module on and off.
2
C Module Mode field sets the operating mode of the

Table 9-6. ICSAR Register

27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
0 0 0 0 0
RO RO RO RW
0xFFFC5000 + 0x04

Table 9-7. ICSAR Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
2
C Module when in
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
SLAD7
0 0 0 0 0
RW RW RW RW RW
2
C Module.
17 16
0 0
RO RO
1 0
0 0
RW RW