Figure 13-2. Usb Clock Divider Chain; Peripheral Block Clocks - Sharp LH79524 User Manual

Reset, Clock, and Power Controller
The RCPC and PLL interface guarantee that reprogramming the PLL and System Clocks
results in an ordely frequency change. For the USB PLL and other clocks, program the
Clock Select and frequency before enabling the peripheral clocks as the RCPC does not
guarantee clean clock outputs when changing the clock source or USB PLL frequency.

13.1.3.2 Peripheral Block Clocks

The USB has two clocks from the RCPC. The System Clock (HCLK) controls AHB trans-
fers and is enabled in the AHBCLKCTRL Register. The second clock originates in the USB
PLL, and is programmed in the RCPC with the PCLKSEL1 and PCLKCTRL 1 registers.
Figure 13-2 schematically shows the progression of the clock divider chain for the USB
Clock, as well as the registers that control each divider and the clock source. The registers
referenced in the figure are defined in Section 13.2.
XTALIN
11.2896 MHz
The RTC clock is generated from the 32.768 kHz crystal oscillator output. The 32.768 kHz
oscillator's output is divided by 32,768 to produce the 1 Hz RTC clock. The UART clocks
are generated from the System Clock crystal oscillator. To activate the RTC and UART
clocks, program the PCLKCTRL0 Register.
The LCD data clock (LCDDCLK) is generated from the System Clock frequency. The SSP
and ADC clocks are generated from either the System Clock or the System Clock Oscilla-
tor clock according to the value programmed in the PCLKSEL1 Register. These clocks are
prescalable according to the values programmed in the SSPPRE Register, LCDPRE Reg-
ister, and ADCPRE Register. To activate these clocks, program the PCLKCTRL1 Register.
Table 13-1 describes each clock and that clock's maximum frequency.
13.1.3.3 External Clock Generation (CLKOUT)
An external clock output signal is availabe on the CLKOUT pin. This signal is capable of
driving 8 mA to external loads. The CLKOUT signal can be programmed to provide one of
three clocks: FCLK, HCLK, or the system crystal oscillator frequency (nominally 11.2896
MHz). Prior to using the CLKOUT signal for external devices, software must choose the
CLKOUT source using the CTRL:OUTSEL field (see Section 13.2.2.1).
13-4
USBPLLCTL:USBPREDIV USBPLLCTL:USBLOOPDIV
USB PLL
CLOCK
PRE-DIVIDER
5 MHz ≤
ƒ ≤ 100 MHz

Figure 13-2. USB Clock Divider Chain

PCLKSEL1:USB
USB REFERENCE
CLOCK
USB CLOCK
USB
PLL
20 MHz ≤
ƒPLL ≤ 305 MHz
(SYSTEM CLOCK)
Version 1.0
LH79524/LH79525 User's Guide
USBPRE:USBDIV
SOURCE PRE-SCALER
SELECT
HCLK
USBCLK
48.0 MHz
±0.25%
LH79525-122