Table 6-28. Phymaint Register; Table 6-29. Phymaint Fields; Phy Maintenance Register (Phymaint) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

6.3.2.12 PHY Maintenance Register (PHYMAINT)

This register enables the EMAC to communicate with a PHY by means of the MDIO inter-
face. It is used during auto negotiation to ensure that the EMAC and the PHY are config-
ured for the same speed and duplex configuration.
The PHY maintenance register is implemented as a shift register. Writing to the
register starts a shift operation, which is signalled as complete when bit two is set in the
NETSTATUS register, about 2,000 HCLK cycles later. An interrupt is also generated.
During this time, the MSB of the register is output on the ETHERMDIO pin and the LSB
updated from the ETHERMDIO pin with each ETHERMDC cycle. This causes transmis-
sion of a PHY management frame on ETHERMDIO. See Section 22.2.4.5 of the IEEE
802.3 standard.
Reading during the shift operation will return the current contents of the shift register. At
the end of management operation, the bits will have shifted back to their original locations.
For a read operation, the data bits will be updated with data read from the PHY.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:30
29:28 OPERATION
27:23
22:18
17:16
15:0

Table 6-28. PHYMAINT Register

31 30 29 28 27
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 6-29. PHYMAINT Fields

NAME
STARTFRM Start Of Frame Must be written 0b01 for a valid frame.
Operation
00 = Invalid
01 = Write
10 = Read
11 = Invalid
PHYADDR Phy Address The PHY address is written to this field.
Register Address Specifies the address of the register in the PHY
REGADDR
to access.
/// Must be written with 0b10. Reads the value written.
PHY Read or Write Data The data to be written to the PHY is contained in
PHYRDWR
these two bytes. For a read, this contains the two bytes read from the PHY.
26 25 24 23
PHYADDR
0 0 0 0
RW RW RW RW
10 9 8 7
PHYRDWR
0 0 0 0
RW RW RW RW
0xFFFC7000 + 0x34
FUNCTION
Version 1.0
Ethernet MAC Controller
22 21 20 19 18
REGADDR
0 0 0 0 0
RW RW RW RW RW
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
///
0 0
RW RW
1 0
0 0
RW RW
6-35