Fschg - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.42

FSCHG

SZ Bit
Inversion
PR
Format
0
FSCHG
1
Description
This instruction inverts the SZ bit in floating-point register FPSCR. Changing the SZ bit in
FPSCR switches FMOV instruction data transfer between one single-precision data unit and a data
pair. When FPSCR.SZ = 0, the FMOV instruction transfers one single-precision data unit. When
FPSCR.SZ = 1, the FMOV instruction transfers two single-precision data units as a pair.
Operation
void FSCHG()
{
if(FPSCR_PR == 0){
FPSCR ^= 0x00100000; /* bit 20 */
PC += 2;
}
else undefined_operation();
}
Possible Exceptions:
None
Rev. 2.0, 03/99, page 282 of 396
Sz-bit CHanGe
Summary of Operation
FRSCR.SZ=~FRSCR.SZ
/* FSCHG */
Floating-Point Instruction
Instruction Code
1111001111111101 1
Execution
States
T Bit

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