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10.21
DMULU.L
Unsigned Double-Length
Multiplication
Format
DMULU.L Rm,Rn
Description
This instruction performs 32-bit multiplication of the contents of general register Rn by the
contents of Rm, and stores the 64-bit result in the MACH and MACL registers. The multiplication
is performed as an unsigned arithmetic operation.
Operation
DMULU(long m, long n)
{
unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
unsigned long temp0,temp1,temp2,temp3;
RnL=R[n]&0x0000FFFF;
RnH=(R[n]>>16)&0x0000FFFF;
RmL=R[m]&0x0000FFFF;
RmH=(R[m]>>16)&0x0000FFFF;
temp0=RmL*RnL;
temp1=RmH*RnL;
temp2=RmL*RnH;
temp3=RmH*RnH;
Res2=0
Res1=temp1+temp2;
if (Res1<temp1) Res2+=0x00010000;
temp1=(Res1<<16)&0xFFFF0000;
Rev. 2.0, 03/99, page 238 of 396
Double-length MULtiply
as Unsigned
Summary of Operation
Unsigned,
Rn × Rm →
MACH, MACL
/* DMULU.L Rm,Rn */
Arithmetic Instruction
Instruction Code
0011nnnnmmmm0101 2–5
Execution
States
T Bit
—
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