Fcmp - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.27

FCMP

Floating-Point
Comparison
PR
Format
1. FCMP/EQ FRm,FRn (FRn==FRm)?1:0 → T
0
2. FCMP/EQ DRm,DRn (DRn==DRm)?1:0 → T
1
3. FCMP/GT FRm,FRn (FRn>FRm)?1:0 → T
0
4. FCMP/GT DRm,DRn (DRn>DRm)?1:0 → T
1
Description
1. When FPSCR.PR = 0: Arithmetically compares the two single-precision floating-point
numbers in FRn and FRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
2. When FPSCR.PR = 1: Arithmetically compares the two double-precision floating-point
numbers in DRn and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
3. When FPSCR.PR = 0: Arithmetically compares the two single-precision floating-point
numbers in FRn and FRm, and stores 1 in the T bit if FRn > FRm, or 0 otherwise.
4. When FPSCR.PR = 1: Arithmetically compares the two double-precision floating-point
numbers in DRn and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise.
Operation
void FCMP_EQ(int m,n) /* FCMP/EQ
{
pc += 2;
clear_cause();
if(fcmp_chk (m,n) == INVALID) fcmp_invalid();
else if(fcmp_chk (m,n) == EQ)
else
}
void FCMP_GT(int m,n) /* FCMP/GT
{
pc += 2;
clear_cause();
if ((fcmp_chk (m,n) == INVALID) ||
(fcmp_chk (m,n) == UO)) fcmp_invalid();
else if(fcmp_chk (m,n) == GT)
Floating-point CoMPare
Summary of Operation Instruction Code
FRm,FRn */
FRm,FRn */
Floating-Point Instruction
1111nnnnmmmm0100 1
1111nnn0mmm00100 1
1111nnnnmmmm0101 2
1111nnn0mmm00101 2
T = 1;
T = 0;
T = 1;
Rev. 2.0, 03/99, page 247 of 396
Execution
States
T Bit
1/0
1/0
1/0
1/0

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