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Hitachi SH7750 Programming Manual page 179

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series

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(e) Flow dependency (cont)

FLOAT FPUL,FR0

FLOAT FPUL,R1

(f) Output dependency

(g) Anti-flow dependency

FMOV @R1,XD0

FADD DR0,DR2

FMOV FR4,FR1

Figure 8.3 Examples of Pipelined Execution (cont)

Effectively 1-cycle latency for consecutive LDS/FLOAT instructions

10 stall cycles = latency (11) - 1

6 stall cycles = longest latency (8) - 2

5 stall cycles

2 stall cycles

Effectively 1-cycle latency for consecutive

FTRC/STS instructions

11-cycle latency

The registers are written-back

in program order.

7-cycle latency for lower FR

8-cycle latency for upper FR

Rev. 2.0, 03/99, page 165 of 396