Boot Flash - GE SBC330 3U VPX Hardware Reference Manual

Errata
May 2011
28 SBC330 3U VPX Single Board Computer
data bus. The Flash in each device is arranged in 256 KByte sectors, has an erase
capacity of 100,000 cycles per sector and typical data retention of 20 years.
NOTE
Integrity of Flash data cannot be guaranteed if a hard reset occurs during a Flash write cycle.
The following table shows the Flash options available for the SBC330:
Table 5-4 Flash Options
Flash Size (MBytes)
256
512 (when available)
The Flash is divided into two contiguous area types: Boot Flash and User Flash.
At least the top 8 MBytes of Flash is reserved for Boot Code (16 MBytes if the Core
1 Boot bit is set in the FPGAʹs Flash Control register). The boot code region is
separated into four 2 MByte boot regions that may be selected using hardware
links. The remainder of the Flash memory is allocated as User Flash.

5.3.4 Boot Flash

Up to 16 MBytes on each of the Flash memory options is taken as Boot Flash, and
is used to hold initialization and operating system boot routines. Each of the two 8
MByte regions can be used to hold up to 4 boot images each for processing cores 0
and 1. However, it is more normal that both processing cores access the same
BootROM. In this case, only the top 8 MBytes is used; core 1 boots from the same
BootROM as core 0 and the rest of Flash is mapped as User Flash.
Figure 5-2 Local Bus CS0 Mapping
Normal four
2 MByte
Boot areas
Core 0 BANC
Spare
Core 0/1 Extended
Core 0/1 Alternate
Core 0/1 Main
User
Flash
CS0
Banks Flash Bank Organization
1 2 x 1024 Mbit
1 2 x 2048 Mbit (when available)
Flash Control
Register 'Core 1
Boot' bit set
0xFFFF FFFF
Core 0 BANC
0xFFFC 0000
Spare
0xFFE0 0000
Core 0 Extended
0xFFC0 0000
Core 0 Alternate
0xFFA0 0000
Core 0 Main
0xFF80 0000
Spare
0xFF60 0000
Core 1 Extended
0xFF40 0000
Core 1 Alternate
0xFF20 0000
Core 1 Main
0xFF00 0000
User
Flash
Not to scale CS0
Publication No. SBC330-0HH/3