Pci Express Infrastructure - GE SBC330 3U VPX Hardware Reference Manual

5.4 PCI Express Infrastructure

Publication No. SBC330-0HH/3
All PCI devices and mezzanine sites on the SBC330 are connected to the
MPC8641D using PCI‐Express (PCIe). The block diagram (Figure 5‐1) shows the
PCIe/PCI structure.
PCIe is a high‐speed serial, point‐to‐point interconnect running at 2.5 Gbits/
second in each direction. PCIe links are scalable, meaning that multiple lanes can
be used between devices to increase the aggregate bandwidth. A comparison of
the bandwidth of PCIe links with PCI implementations are shown in the table
below.
Table 5-6 PCI Bus
Bus Type Bus Width
PCI 32-bit
PCI 32-bit
PCI 64-bit
PCI-X 64-bit
PCIe x1
PCIe x2
PCIe x4
PCIe x8
NOTE
PCIe bandwidths shown include 8b/10b encoding overheads.
PCIe is a packet‐based protocol, but uses the same address spaces as standard
PCI, so the software interfaces are backwards‐compatible. PCIe‐to‐PCI Bridges
are used to convert to PCI‐X or standard PCI where connection to these devices is
required.
The maximum packet payload size for the PCI Express sub‐system is 256 Bytes.
CRC error‐checking is performed on each packet transmitted between devices in
the system and any corrupted packets are retransmitted. The target device can
also perform end‐to‐end error checking to ensure integrity of the received data.
All 8 lanes of PCIe from port 2 are routed directly to the VPX connector. This link
supports very high bandwidth peripheral cards such as the GEIP GRA110
graphics processor.
All 8 lanes of PCIe from port 1 are routed to a PLX PEX8518 Switch device. This
routes 4 lanes externally and can be set up via an associated SPI EEPROM to make
the PCIe port transparent (the default) or non transparent to allow for
communication with other intelligent devices or end‐point peripherals.
The switch additionally routes 2 lanes to a PLX PEX8114 PCIe to PCI Bridge
device, and 1 lane to a Silicon Image si3132 dual SATA device. The PEX8114
Bridge is used to connect the processor to the NEC uPD72, which in turn connects
to a NEC uPD720101 4‐port USB device.
NOTE
If two SBC330 boards are connected together, it is possible, given BSP support that Rapid-IO (sRIO)
could be run as a protocol as opposed to PCIe. Contact GEIP for more details.
Bandwidth
Frequency
(MBytes/sec)
33 MHz 133
66 MHz 266
66 MHz 533
133 MHz 1066
2.5 Gbps 250
2.5 Gbps 500
2.5 Gbps 1000
2.5 Gbps 2000
Notes
Sn
Per Direction
Per Direction
Per Direction
Per Direction
Functional Description 31