GE 90*-30 PLC Series User Manual page 70

PLC I/O Table Mapping
Method
Reference Parameters
Module Input/Output
Offsets in PLC CPU I/O
Tables
PLC I/O Table to NV
Mapping
PLC Register to NV
Array Mapping
Data Coherency
Fast updates
Valid Bit
Module Control %I
locations
GFK-1322A
Table C-5. PLC I/O Table Configuration
Defined using Parameter 0.
1 - The parameter 0 register setup will be used. In addition, an enumerated text parameter will be
used as parameter 1. The text will contain: "Last Parameter"
Specified in the custom area of the self documentation string for the node.
This will consist of:
. %I start, len
%AI start, len
%Q start, len
%AQ start, len
%V start, len.
where:
"." is the start/end of the address description
"start" is the starting CPU I/O table offset for each memory type (max. 5 digits).
"len" is the number of memory locations used by this module.
%V specifies the start and length of the valid bit block in the %I I/O table.
Specified in the custom area of the self documentation string for each network variable. This will
consist of:
.%mType start, len, valid, default.
where:
"." is the start / end of the map desc.
"mType" is I, Q, AI, or AQ
"start" is the starting CPU I/O table offset for the memory type (max. 5 digits).
"len" is the number of I/O table locations used by this NV.
"valid" is the %I CPU I/O table offset of the valid bit for the network variable.
"default" is either H or 0. This is used when the LBIM detects the network interface is down, where:
H - Leave value sent to the PLC as is.
0 - Set the value to the PLC to zero.
Default only applies to input network variables.
An NV array has one declaration in the .XIF file and therefore has only one mapping description in
the self-documentation string. The size of the IO Table data will be the size of the NV element times
the number of NV array elements.
The PLC must update all memory locations for a network variable in a single sweep to stop
intermittent values from propagating over the network. Data Coherency must be maintained over
each network variable.
If the PLC updates memory locations faster than the LBIM can update the NV or the network can
propagate the NV, will result in those transitions being lost.
Each network variable is configured to have a valid bit in the %I I/O table. For input NVs, the bit
will be set if the NV has been updated and the Max Receive Time (if set) has not expired. For
output NVs, the bit will be set if the NV has been propagated and a failure not been detected (must
use acknowledged service).
8 bits of %I registers (mapped to first location).
Bit 1: L W interface running.
ON ORKS
Bit 2: Network variable mapping configured.
Bits 3-8: reserved for future use
Appendix C Configuration File Specifications
C
C-3