Mode, Osc Enable, Boot Eeprom Select, And Addr Select Dip Switch S2 - Xilinx ML605 User Manual

Chapter 1: ML605 Evaluation Board

Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2

DIP switch S2 is a multi-purpose selector switch
FPGA Mode: S2 switches 3, 4, and 5 control the FPGA mode
Oscillator Enable: S2 switch 1, CCLK_EXTERNAL, controls the enable pin of the 47 MHz
oscillator SiT8102 (X4). When switch 1 is closed (CCLK_EXTERNAL High), X4 drives a
47 MHz clock onto the FPGA_CCLK signal.
Boot EEPROM Select: S2 switch 2 is used to select the between the Xilinx Platform Flash or
the Numonyx Linear BPI Flash for the FPGA boot memory device.
Upper or Lower Address Select: S2 switch 6 is used to select the upper or lower half of
flash memory U4 as the source of the FPGA bitstream image. When FLASH_A23 is High,
the upper half of the address is selected. When FLASH_A23 is Low, the lower half of the
address is selected.
X-Ref Target - Figure 1-27
Table 1-26
Table 1-26: ML605 Configuration Modes
Configuration Mode
56
VCC2V5
1 1 1
2 2 2
Figure 1-27: Multi-Purpose Select DIP Switch S2
shows the FPGA configuration modes controlled by S2 switches 3, 4, and 5.
Master BPI-Up
JTAG
Slave SelectMAP
www.xilinx.com
(Figure 1-27
S2
7
6
8
5
9
4
10
3
11
2
12
1
SDMX-6-X
1 1
2 2
M[2:0] Bus Width
010 8, 16
101 1
110 8, 16, 32
and Table 1-27, page
(Table 1-26).
FLASH_A23
FPGA_M2
FPGA_M1
FPGA_M0
P30_CS_SEL
CCLK EXTERNAL
1 1 1 1
2 2 2 2
UG534_27_110409
CCLK
Output
Input (TCK)
Input
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010
57).