GigaDevice Semiconductor GD32F30 Series User Manual page 838

Arm cortex-m4 32-bit mcu
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Global receive FIFO length register (USBFS_GRFLEN)
Address offset: 0x024
Reset value: 0x0000 0200
This register has to be accessed by word (32-bit)
31
30
29
15
14
13
Bits
Fields
31:16
Reserved
15:0
RXFD[15:0]
Host non-periodic transmit FIFO length register /Device IN endpoint 0 transmit
FIFO length (USBFS_HNPTFLEN _DIEP0TFLEN)
Address offset: 0x028
Reset value: 0x0200 0200
This register has to be accessed by word (32-bit)
31
30
29
15
14
13
Host Mode:
28
27
26
25
12
11
10
9
Descriptions
Must be kept at reset value
Rx FIFO depth
In terms of 32-bit words.
1≤RXFD≤1024
28
27
26
25
12
11
10
9
GD32F30x User Manual
24
23
22
21
8
7
6
5
r/rw
24
23
22
21
r/rw
8
7
6
5
r/rw
20
19
18
17
4
3
2
1
20
19
18
17
4
3
2
1
16
0
16
0
838

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