System Architecture; Figure 1-1. The Structure Of The Cortex; Table 1-1. The Interconnection Relationship Of The Ahb Interconnect Matrix - GigaDevice Semiconductor GD32F30 Series User Manual

Figure 1-1. The structure of the Cortex

Interrupts and
Power control
Wake-up
Interrupt
Controller
(WIC)
Serial-Wire
Or JTAG
Debug Port
(SWDP or SWJ-
DP)
Serial-Wire or
JTAG Debug
Interface
1.2.

System architecture

A 32-bit multilayer bus is implemented in the GD32F30x devices, which enables parallel
access paths between multiple masters and slaves in the system. The multilayer bus consists
of an AHB interconnect matrix, one AHB bus and two APB buses. The interconnection
relationship of the AHB interconnect matrix is shown below. In the f ollowing table, "1" indicates
the corresponding master is able to access the corresponding slave through the AHB
interconnect matrix, while the blank means the corresponding master cannot access the
corresponding slave through the AHB interconnect matrix.

Table 1-1. The interconnection relationship of the AHB interconnect matrix

FMC-I
FMC-D
SRAM
EXMC
Nested
Vectored
Interrupt
Controller
(NVIC)
Flash Patch
Breakpoint
(FPB)
AHB
Access port
(AHB-AP)
ICode
AHB-Lite
Data
interface
IBUS DBUS SBUS DMA0 DMA1
1
1
1 1 1
1 1 1
GD32F30x User Manual
®
-M4 processor
Cortex-M4 processor
Cortex-M4 core
Floating Point
Unit(FPU)
Memory
Protection
Unit(MPU)
Bus Matrix
DCode System
AHB-Lite AHB-Lite
Data System
interface interface
ENET
1 1
1 1 1
1 1 1
Data
Watchpoint
And Trace
(DWT)
Instrumentation
Trace Macrocell Interface Unit
(ITM)
CoreSight
PPB APB
ROM table
Debug system
interface
Trace Port
(TPIU)
Trace Port
Interface
31