GigaDevice Semiconductor GD32F190 Series Manuals

Manuals and User Guides for GigaDevice Semiconductor GD32F190 Series. We have 2 GigaDevice Semiconductor GD32F190 Series manuals available for free PDF download: User Manual

GigaDevice Semiconductor GD32F190 Series User Manual (702 pages)

ARM Cortex-M3 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 9.64 MB

Table of Contents
2
List of Figures
17
List of Tables
24
System and Memory Architecture
27
ARM Cortex-M3 Processor
27
System Architecture
28
Figure 1-1. the Structure of the Cortex
28
Figure 1-2. Series System Architecture of Gd32F130Xx and Gd32F150Xx Devices
29
Memory Map
30
Figure 1-3. Series System Architecture of Gd32F170Xx and Gd32F190Xx Devices
30
Table 1-1. Memory Map of Gd32F130Xx and Gd32F150Xx Devices
31
Table 1-2. Memory Map of Gd32F170Xx and Gd32F190Xx Devices
33
Bit-Banding
35
On-Chip SRAM Memory
35
On-Chip Flash Memory
36
Boot Configuration
36
Table 1-3. Flash Module Organization
36
Table 1-4. Boot Modes
36
System Configuration Registers (SYSCFG)
38
System Configuration Register 0 (SYSCFG_CFG0)
38
System Configuration Register 1 (SYSCFG_CFG1)
39
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
39
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
41
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
42
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
43
System Configuration Register 2 (SYSCFG_CFG2)
44
Device Electronic Signature
45
Memory Density Information
46
Unique Device ID (96 Bits)
46
Flash Memory Controller (FMC)
48
Overview
48
Characteristics
48
Function Overview
48
Flash Memory Architecture
48
Table 2-1. Base Address and Size for Flash Memory
48
Read Operations
49
Unlock the FMC_CTL Register
49
Page Erase
49
Mass Erase
50
Figure 2-1. Process of Page Erase Operation
50
Figure 2-2. Process of the Mass Erase Operation
51
Main Flash Programming
52
Option Bytes Erase
53
Figure 2-3. Process of the Word Programming Operation
53
Option Bytes Programming
54
Option Bytes Description
54
Table 2-2. Option Bytes
54
Page Erase/Program Protection
55
Security Protection
56
Table 2-3. OB_WP Bit for Pages Protected
56
Register Definition
57
Wait State Register (FMC_WS)
57
Unlock Key Register (FMC_KEY)
57
Option Bytes Unlock Key Register (FMC_OBKEY)
58
Status Register (FMC_STAT)
58
Control Register (FMC_CTL)
59
Address Register (FMC_ADDR)
60
Option Bytes Status Register (FMC_OBSTAT)
61
Write Protection Register (FMC_WP)
61
Wait State Enable Register (FMC_WSEN)
62
Product ID Register (FMC_PID)
63
Power Management Unit (PMU)
64
Overview
64
Characteristics
64
Function Overview
64
Figure 3-1. Power Supply Overview of Gd32F130Xx and Gd32F150Xx Devices
65
Backup Domain
66
Figure 3-2. Power Supply Overview of Gd32F170Xx and Gd32F190Xx Devices
66
Dda
67
VDD Domain
67
Figure 3-3. Waveform of the POR/PDR
68
1.2V Power Domain for Gd32F130Xx and Gd32F150Xx Devices
69
1.8V Power Domain for Gd32F170Xx and Gd32F190Xx Devices
69
Figure 3-4. Waveform of LVD Threshold
69
Power Saving Modes
70
Table 3-1. Power Saving Mode Summary
71
Register Definition
72
Control Register (PMU_CTL)
72
Power Control/Status Register (PMU_CS)
75
Reset and Clock Unit (RCU)
77
Reset Control Unit (RCTL)
77
Overview
77
Function Overview
77
Clock Control Unit (CCTL)
78
Overview
78
Figure 4-1. the System Reset Circuit
78
Figure 4-2. Clock Tree of Gd32F130Xx and Gd32F150Xx Devices
79
Figure 4-3. Clock Tree of Gd32F170Xx and Gd32F190Xx Devices
80
Characteristics
81
Function Overview
81
Figure 4-4. HXTAL Clock Source
81
Table 4-1. Clock Source Select
84
Table 4-2. Clock Source Select
84
Table 4-3. Core Domain Voltage Selected in Deep-Sleep Mode
85
Table 4-4. Core Domain Voltage Selected in Deep-Sleep Mode
85
Register Definition
86
Control Register 0 (RCU_CTL0)
86
Configuration Register 0 (RCU_CFG0)
87
Interrupt Register (RCU_INT)
94
APB2 Reset Register (RCU_APB2RST)
100
APB1 Reset Register (RCU_APB1RST)
101
AHB Enable Register (RCU_AHBEN)
106
APB2 Enable Register (RCU_APB2EN)
107
APB1 Enable Register (RCU_APB1EN)
109
Backup Domain Control Register (RCU_BDCTL)
113
Reset Source /Clock Register (RCU_RSTSCK)
116
AHB Reset Register (RCU_AHBRST)
118
Configuration Register 1 (RCU_CFG1)
119
Configuration Register 2 (RCU_CFG2)
120
Control Register 1 (RCU_CTL1)
122
Configuration Register 3 (RCU_CFG3) of Gd32F170Xx and Gd32F190Xx Devices
123
APB1 Additional Enable Register (RCU_ADDAPB1EN)
124
APB1 Additional Reset Register (RCU_ADDAPB1RST)
124
Voltage Key Register (RCU_VKEY)
125
Deep-Sleep Mode Voltage Register (RCU_DSV)
125
Power down Voltage Select Register (RCU_PDVSEL) of Gd32F130Xx and Gd32F150Xx Devices
126
Interrupt/Event Controller (EXTI)
128
Overview
128
Characteristics
128
Interrupts Function Overview
128
Table 5-1. NVIC Exception Types in Cotrex-M3
129
Table 5-2. Interrupt Vector Table of Gd32F130Xx and Gd32F150Xx Devices
129
Table 5-3. Interrupt Vector Table of Gd32F170Xx and Gd32F190Xx Devices
130
External Interrupt and Event (EXTI) Block Diagram
132
Figure 5-1. Block Diagram of EXTI
132
External Interrupt and Event Function Overview
133
Table 5-4. EXTI Source of Gd32F130Xx and Gd32F150Xx Devices
133
Table 5-5. EXTI Source of Gd32F170Xx and Gd32F190Xx Devices
134
Register Definition
136
Interrupt Enable Register (EXTI_INTEN)
136
Event Enable Register (EXTI_EVEN)
136
Rising Edge Trigger Enable Register (EXTI_RTEN)
137
Falling Edge Trigger Enable Register (EXTI_FTEN)
137
Software Interrupt Event Register (EXTI_SWIEV)
138
Pending Register (EXTI_PD)
139
General-Purpose I/Os (GPIO)
140
Overview
140
Characiteristics
140
Function Overview
140
GPIO Pin Configuration
141
Figure 6-1. Basic Structure of a General-Pupose I/O
141
Table 6-1. GPIO Configuration Table
141
Alternate Functions (AF)
142
Additional Functions
142
Input Configuration
142
Figure 6-2. Basic Structure of Input Configuration
142
Output Configuration
143
Figure 6-3. Basic Structure of Output Configuration
143
Analog Configuration
144
Alternate Function (AF) Configuration
144
Figure 6-4. Basic Structure of Analog Configuration
144
Figure 6-5. Basic Structure of Alternate Function Configuration
144
GPIO Locking Function
145
GPIO Single Cycle Toggle Function
145
Register Definition
146
Port Control Register (Gpiox_Ctl, X=A
146
Port Output Mode Register (Gpiox_Omode, X=A
147
Port Output Speed Register (Gpiox_Ospd, X=A
149
Port Pull-Up/Down Register (Gpiox_Pud, X=A
151
Port Input Status Register (Gpiox_Istat, X=A
152
Port Output Control Register (Gpiox_Octl, X=A
153
Port Bit Operate Register (Gpiox_Bop, X=A
153
Port Configuration Lock Register (Gpiox_Lock, X=A, B)
154
Alternate Function Selected Register0 (Gpiox_Afsel0, X=A, B, C)
155
Alternate Function Selected Register1 (Gpiox_Afsel1, X=A,B,C)
156
Bit Clear Register (Gpiox_Bc, X=A
157
Port Bit Toggle Register (Gpiox_Tg, X=A
158
Cyclic Redundancy Checks Management Unit (CRC)
159
Overview
159
Characteristics
159
Function Overview
160
Figure 7-1. Block Diagram of CRC Management Unit
160
Register Definition
162
Data Register (CRC_DATA)
162
Free Data Register (CRC_FDATA)
162
Control Register (CRC_CTL)
163
Initialization Data Register (CRC_IDATA)
163
Direct Memory Access Controller (DMA)
165
Overview
165
Characteristics
165
Block Diagram
166
Function Overview
166
DMA Operation
166
Figure 8-1. Block Diagram of DMA
166
Table 8-1. DMA Transfer Operation
167
Peripheral Handshake
168
Arbitration
168
Figure 8-2. Handshake Mechanism
168
Address Generation
169
Circular Mode
169
Memory to Memory Mode
169
Channel Configuration
169
Interrupt
170
Figure 8-3. DMA Interrupt Logic
170
Table 8-2. Interrupt Events
170
DMA Request Mapping
171
Table 8-3. DMA Requests for each Channel
171
Figure 8-4. DMA Request Mapping
172
Register Definition
174
Interrupt Flag Register (DMA_INTF)
174
Interrupt Flag Clear Register (DMA_INTC)
174
Channel X Control Register (Dma_Chxctl)
175
Channel X Counter Register (Dma_Chxcnt)
177
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
178
Channel X Memory Base Address Register (Dma_Chxmaddr)
178
Debug (DBG)
180
Overview
180
Serial Wire Debug Port Overview
180
Pin Assignment
180
JEDEC-106 ID Code
180
Debug Hold Function Overview
181
Debug Support for Power Saving Mode
181
Debug Support for TIMER, I2C, RTC, WWDGT and FWDGT
181
DBG Registers
182
ID Code Register (DBG_ID)
182
Control Register 0(DBG_CTL0)
182
Control Register 1 (DBG_CTL1)
186
Analog to Digital Converter (ADC)
188
Overview
188
Characteristics
188
Pins and Internal Signals
189
Figure 10-1. ADC Module Block Diagram of Gd32F130Xx and Gd32F150Xx Devices
189
Figure 10-2. ADC Module Block Diagram of Gd32F170Xx and Gd32F190Xx Devices
189
Table 10-1. ADC Internal Input Signals
190
Table 10-2. ADC Input Pins Definition of Gd32F130Xx and Gd32F150Xx Devices
190
Table 10-3. ADC Input Pins Definition of Gd32F170Xx and Gd32F190Xx Devices
190
Function Overview
191
Foreground Calibration Function
192
Dual Clock Domain Architecture
193
ADCON Enable
193
Routine Sequence
193
Operation Modes
193
Figure 10-3. Single Operation Mode
193
Figure 10-4. Continuous Operation Mode
194
Figure 10-5. Scan Operation Mode, Continuous Disable
195
Figure 10-6. Scan Operation Mode, Continuous Enable
195
Conversion Result Threshold Monitor Function
196
Data Storage Mode
196
Figure 10-7. Discontinuous Operation Mode
196
Sample Time Configuration
197
Figure 10-8. Data Storage Mode of 12-Bit Resolution
197
Figure 10-9. Data Storage Mode of 10-Bit Resolution
197
Figure 10-10. Data Storage Mode of 8-Bit Resolution
197
Figure 10-11. Data Storage Mode of 6-Bit Resolution
197
External Trigger Configuration
198
DMA Request
198
ADC Internal Channels
198
Table 10-4. External Trigger Source for ADC Routine Sequence
198
Battery Voltage Monitoring
199
ADC Interrupts
199
Programmable Resolution (DRES)
199
Table 10-5. T CONV Timings Depending on Resolution
199
On-Chip Hardware Oversampling
200
Figure 10-12. 20-Bit to 16-Bit Result Truncation
200
Figure 10-13. Numerical Example with 5-Bits Shift and Rounding
200
Table 10-6. Maximum Output Results Vs N and M (Grayed Values Indicates Truncation)
201
Register Definition
203
Status Register (ADC_STAT)
203
Control Register 0 (ADC_CTL0)
203
Control Register 1 (ADC_CTL1)
206
Sampling Time Register 0 (ADC_SAMPT0)
208
Sampling Time Register 1 (ADC_SAMPT1)
210
Watchdog High Threshold Register (ADC_WDHT)
211
Watchdog Low Threshold Register (ADC_WDLT)
211
Routine Sequence Register 0 (ADC_RSQ0)
212
Routine Sequence Register 1 (ADC_RSQ1)
212
Routine Sequence Register 2 (ADC_RSQ2)
213
Routine Data Register (ADC_RDATA)
213
Oversampling Control Register (ADC_OVSAMPCTL)
214
Digital-To-Analog Converter (DAC)
216
Overview
216
Characteristic
216
Figure 11-1. DAC Block Diagram
216
Function Overview
217
DAC Enable
217
DAC Output Buffer
217
Table 11-1. DAC I/O Description
217
DAC Data Configuration
218
DAC Trigger
218
Table 11-2. External Triggers of DAC
218
DAC Workflow
219
DAC Output Calculate
219
DMA Function
219
DAC Concurrent Conversion for Gd32F190Xx Devices
219
Register Definition
221
Control Register (DAC_CTL)
221
Software Trigger Register (DAC_SWT)
224
DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12DH)
225
DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12DH)
225
DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8DH)
226
DAC1 12-Bit Right-Aligned Data Holding Register (DAC1_R12DH) of Gd32F190Xx Devices
226
DAC1 12-Bit Left-Aligned Data Holding Register (DAC1_L12DH) of Gd32F190Xx Devices
227
DAC1 8-Bit Right-Aligned Data Holding Register (DAC1_R8DH) of Gd32F190Xx Devices
227
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH) of
228
Gd32F190Xx Devices
228
Gd32F190Xx Devices
229
DAC0 Data Output Register (DAC0_DO)
230
DAC1 Data Output Register (DAC1_DO) of Gd32F190Xx Devices
230
Status Register (DAC_STAT)
230
Comparator (CMP)
233
Overview
233
Characteristics
233
Function Overview
233
Figure 12-1. CMP Block Diagram of Gd32F150Xx Devices
234
Figure 12-2. CMP Block Diagram of Gd32F190Xx Devices
234
CMP Clock and Reset
235
CMP I/O Configure
235
CMP Operating Mode
235
CMP Hysteresis
235
CMP Register Write Protection
236
Figure 12-3. CMP Hysteresis
236
Register Definition
237
Control/Status Register (CMP_CS)
237
Watchdog Timer (WDGT)
244
Free Watchdog Timer (FWDGT)
244
Overview
244
Characteristics
244
Function Overview
244
Figure 13-1. Free Watchdog Timer Block Diagram
245
Table 13-1. Min / Max FWDGT Timeout Period at 40 Khz (IRC40K)
246
Register Definition
247
Window Watchdog Timer (WWDGT)
251
Overview
251
Characteristics
251
Function Overview
251
Figure 13-2. Window Watchdog Timer Block Diagram
252
Figure 13-3. Window Watchdog Timer Timing Diagram
253
Table 13-2. Min-Max Timeout Value at 36 Mhz (Fpclk1)
253
Register Definition
254
Real-Time Clock(RTC)
256
Overview
256
Characteristics
256
Function Overview
257
Block Diagram
257
Clock Source and Prescalers
257
Figure 14-1. Block Diagram of RTC
257
Shadow Registers Introduction
258
Configurable and Field Maskable Alarm
258
RTC Initialization and Configuration
259
Calendar Reading
260
Resetting the RTC
261
RTC Shift Function
261
RTC Reference Clock Detection
262
RTC Smooth Digital Calibration
263
Time-Stamp Function
265
Tamper Detection
265
Calibration Clock Output
266
Alarm Output
266
RTC Power Saving Mode Management
267
RTC Interrupts
267
Table 14-1. RTC Power Saving Mode Management
267
Table 14-2. RTC Interrupts Control
267
Register Definition
268
Time Register (RTC_TIME)
268
Date Register (RTC_DATE)
268
Control Register (RTC_CTL)
269
Status Register (RTC_STAT)
271
Prescaler Register (RTC_PSC)
273
Alarm 0 Time and Date Register (RTC_ALRM0TD)
274
Write Protection Key Register (RTC_WPK)
275
Sub Second Register (RTC_SS)
275
Shift Function Control Register (RTC_SHIFTCTL)
276
Time of Time Stamp Register (RTC_TTS)
276
Date of Time Stamp Register (RTC_DTS)
277
Sub Second of Time Stamp Register (RTC_SSTS)
278
High Resolution Frequency Compensation Register (RTC_HRFC)
278
Tamper Register (RTC_TAMP)
279
Alarm 0 Sub Second Register (RTC_ALRM0SS)
281
Backup Registers (Rtc_Bkpx) (X=0
282
Timer (Timerx)
284
Table 15-1. Timers (Timerx) Are Devided into Six Sorts
284
Advanced Timer (Timerx,X=0)
285
Overview
285
Characteristics
285
Block Diagram
286
Function Overview
286
Figure 15-1. Advanced Timer Block Diagram
286
Figure 15-2. Timing Chart of Internal Clock Divided by 1
287
Figure 15-3. Timing Chart of PSC Value Change from 0 to 2
288
Figure 15-4. Timing Chart of up Counting Mode, PSC=0/2
289
Figure 15-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
289
Figure 15-6. Timing Chart of down Counting Mode, PSC=0/2
290
Figure 15-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
291
Figure 15-8. Center-Aligned Counter Timechart
291
Figure 15-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode
293
Figure 15-10. Repetition Counter Timing Chart of up Counting Mode
293
Figure 15-11. Repetition Counter Timing Chart of down Counting Mode
294
Figure 15-12. Channel Input Capture Principle
295
Figure 15-13. Channel Output Compare Principle (with Complementary Output
296
Figure 15-14. Channel Output Compare Principle (CH3_O)
296
Figure 15-15. Output-Compare under Three Modes
297
Figure 15-16. EAPWM Timechart
299
Figure 15-17. CAPWM Timechart
299
Table 15-2. Complementary Outputs Controlled by Parameters
300
Figure 15-18. Channel Output Complementary PWM with Dead-Time Insertion
302
Figure 15-19. Output Behavior in Response to a Break(the Break High Active)
303
Table 15-3. Counting Direction Versus Encoder Signals
303
Figure 15-20. Example of Counter Operation in Encoder Interface Mode
304
Figure 15-21. Example of Encoder Interface Mode with CI0FE0 Polarity Inverted
304
Figure 15-22. Hall Sensor Is Used to BLDC Motor
304
Figure 15-23. Hall Sensor Timing between Two Timers
306
Table 15-4. Slave Mode Example Table
306
Figure 15-24. Restart Mode
307
Figure 15-25. Pause Mode
307
Figure 15-26. Event Mode
308
Figure 15-27. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
309
Figure 15-28. TIMER0 Master/Slave Mode Timer Example
309
Table 15-5. Input Trigger of Timer0
310
Figure 15-29. Triggering TIMER0 with Enable of TIMER2
311
Figure 15-30. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input
312
Timerx Registers(X=0)
313
General Level0 Timer (Timerx, X=1, 2)
341
Overview
341
Characteristics
341
Block Diagram
341
Figure 15-31. General Level 0 Timer Block Diagram
341
Function Overview
342
Figure 15-32. Timing Chart of Internal Clock Divided by 1
343
Figure 15-33. Timing Chart of PSC Value Change from 0 to 2
344
Figure 15-34. Timing Chart of up Counting Mode, PSC=0/2
344
Figure 15-35. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
345
Figure 15-36. Timing Chart of down Counting Mode, PSC=0/2
346
Figure 15-37. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
347
Figure 15-38. Center-Aligned Counter Timechart
347
Figure 15-39. Channel Input Capture Principle
349
Figure 15-40. Channel Output Compare Principle (X=0,1,2,3)
350
Figure 15-41. Output-Compare under Three Modes
351
Figure 15-42. Timing Chart of EAPWM
351
Figure 15-43. Timing Chart of CAPWM
352
Table 15-6. Timerx(X=1,2) Interconnection
353
Timerx Registers(X=1, 2)
355
General Level2 Timer (Timerx, X=13)
381
Overview
381
Characteristics
381
Block Diagram
381
Figure 15-44. General Level2 Timer Block Diagram
381
Function Overview
382
Figure 15-45. Timing Chart of Internal Clock Divided by 1
383
Figure 15-46. Timing Chart of PSC Value Change from 0 to 2
383
Figure 15-47. Timing Chart of up Counting Mode, PSC=0/2
384
Figure 15-48. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
385
Figure 15-49. Channel Input Capture Principle
386
Figure 15-51. Output-Compare under Three Modes
388
Figure 15-52. PWM Mode Timechart
388
Timerx Registers(X=13)
390
General Level3 Timer (Timerx, X=14)
401
Overview
401
Characteristics
401
Block Diagram
401
Figure 15-53. General Level3 Timer Block Diagram
401
Figure 15-54. Timing Chart of Internal Clock Divided by 1
403
Figure 15-55. Timing Chart of PSC Value Change from 0 to 2
404
Figure 15-56. Timing Chart of up Counting Mode, PSC=0/2
405
Figure 15-57. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
405
Figure 15-58. Repetition Counter Timing Chart of up Counting Mode
406
Figure 15-59. Channel Input Capture Principle
407
Figure 15-50. Channel Output Compare Principle
408
Figure 15-60. Channel Output Compare Principle (with Complementary Output, X=0)
408
Figure 15-61. Channel Output Compare Principle (CH1_O)
408
Figure 15-62. Output-Compare under Three Modes
409
Figure 15-63. PWM Mode Timechart
410
Table 15-7. Complementary Outputs Controlled by Parameters
412
Figure 15-64. Complementary Output with Dead-Time Insertion
413
Figure 15-65. Output Behavior in Response to a Break(the Break High Active)
414
Table 15-8. Slave Mode Example Table
414
Figure 15-66. Restart Mode
415
Figure 15-67. Pause Mode
415
Figure 15-68. Event Mode
416
Figure 15-69. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
416
Table 15-9. Timerx(X=14) Interconnection
417
Figure 15-70. General Level4 Timer Block Diagram
438
Figure 15-71. Timing Chart of Internal Clock Divided by 1
440
Figure 15-72. Timing Chart of PSC Value Change from 0 to 2
440
Figure 15-73. Timing Chart of up Counting Mode, PSC=0/2
441
Figure 15-74. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
442
Figure 15-75. Repetition Counter Timing Chart of up Counting Mode
443
Figure 15-76. Channel Input Capture Principle
444
Figure 15-77. Output-Compare under Three Modes
445
Figure 15-78. PWM Mode Timechart
446
Table 15-10. Complementary Outputs Controlled by Parameters
448
Figure 15-79. Channel Output Complementary PWM with Dead-Time Insertion
449
Figure 15-80. Output Behavior in Response to a Break(the Break High Active)
450
Figure 15-81. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
451
Figure 15-82. Basic Timer Block Diagram
468
Figure 15-83. Timing Chart of Internal Clock Divided by 1
469
Figure 15-84. Timing Chart of PSC Value Change from 0 to 2
470
Figure 15-85. Timing Chart of up Counting Mode, PSC=0/2
471
Figure 15-86. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
471
Figure 16-1. IFRP Output Timechart 1
478
Figure 16-2. IFRP Output Timechart 2
479
Figure 16-3. IFRP Output Timechart 3
479
Figure 17-1. USART Module Block Diagram
482
Table 17-1. USART Important Pins Description
482
Figure 17-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
483
Table 17-2. Stop Bits Configuration
483
Figure 17-3. USART Transmit Procedure
485
Figure 17-4. Oversampling Method of a Receive Frame Bit (OSB=0)
486
Figure 17-5. Configuration Step When Using DMA for USART Transmission
487
Figure 17-6. Configuration Step When Using DMA for USART Reception
488
Figure 17-7. Hardware Flow Control between Two Usarts
488
Figure 17-8. Hardware Flow Control
489
Figure 17-9. Break Frame Occurs During Idle State
490
Figure 17-10. Break Frame Occurs During a Frame
491
Figure 17-11. Example of USART in Synchronous Mode
491
Figure 17-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
492
Figure 17-13. Irda SIR ENDEC Module
492
Figure 17-14. Irda Data Modulation
493
Figure 17-15. ISO7816-3 Frame Format
494
Table 17-3. USART Interrupt Requests
496
Figure 17-16. USART Interrupt Mapping Diagram
497
Figure 18-1. I2C Module Block Diagram
516
Table 18-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
517
Figure 18-2. Data Validation
518
Figure 18-3. START and STOP Signal
518
Figure 18-4. Clock Synchronization
519
Figure 18-5. SDA Line Arbitration
519
Figure 18-6. I2C Communication Flow with 7-Bit Address
520
Figure 18-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
520
Figure 18-8. I2C Communication Flow with 10-Bit Address (Master Receive)
520
Figure 18-9. Programming Model for Slave Transmitting (10-Bit Address Mode)
520
Figure 18-10. Programming Model for Slave Receiving (10-Bit Address Mode)
522
Figure 18-11. Programming Model for Master Transmitting (10-Bit Address Mode)
523
Figure 18-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)
527
Figure 18-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)
528
Table 18-2. Event Status Flags
532
Table 18-3. Error Flags
533
Figure 19-1. Block Diagram of SPI for Gd32F130Xx and Gd32F150Xx Devices
546
Figure 19-2. Block Diagram of SPI for Gd32F170Xx and Gd32F190Xx Devices
546
Table 19-1. SPI Signal Description
546
Table 19-2. Quad-SPI Signal Description
547
Figure 19-3. SPI Timing Diagram in Normal Mode
548
Figure 19-4. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0) for Gd32F170Xx and Gd32F190Xx Devices
548
Table 19-3. NSS Function in Slave Mode
549
Table 19-4. NSS Function in Master Mode
549
Table 19-5. SPI Operation Modes
550
Figure 19-5. a Typical Full-Duplex Connection
551
Figure 19-6. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
551
Figure 19-7. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
551
Figure 19-8. a Typical Bidirectional Connection
552
Figure 19-9. Timing Diagram of Write Operation in Quad-SPI Mode
554
Figure 19-10. Timing Diagram of Read Operation in Quad-SPI Mode
555
Table 19-6. SPI Interrupt Requests
557
Figure 19-11. Block Diagram of I2S
558
Figure 19-12. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
559
Figure 19-13. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
559
Figure 19-14. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
559
Figure 19-15. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
560
Figure 19-16. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
560
Figure 19-17. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
560
Figure 19-18. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
560
Figure 19-19. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
561
Figure 19-20. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
561
Figure 19-21. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
561
Figure 19-22. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
561
Figure 19-23. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
561
Figure 19-24. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
562
Figure 19-25. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
562
Figure 19-26. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
562
Figure 19-27. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
562
Figure 19-28. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
562
Figure 19-29. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
563
Figure 19-30. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
563
Figure 19-31. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
563
Figure 19-32. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
563
Figure 19-33. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
564
Figure 19-34. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
564
Figure 19-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
564
Figure 19-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
564
Figure19-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
564
Figure 19-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
565
Figure 19-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
565
Figure 19-40. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
565
Figure19-41. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
565
Figure 19-42. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
565
Figure 19-43. PCM Standard Long Frame Synchronization Mode Timing Diagram
565
Figure 19-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
566
Figure 19-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
566
Figure 19-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
566
Figure 19-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
566
Figure 19-48. Block Diagram of I2S Clock Generator
567
Table 19-7. I2S Bitrate Calculation Formulas
567
Table 19-8. Audio Sampling Frequency Calculation Formulas
567
Figure 19-49. I2S Initialization Sequence
568
Table 19-9. Direction of I2S Interface Signals for each Operation Mode
568
Figure 19-50. I2S Master Reception Disabling Sequence
571
Table 19-10. I2S Interrupt
573
Figure 20-1. HDMI-CEC Controller Block Diagram
585
Figure 20-2. Message Structure
585
Table 20-1. Frame Structure
585
Figure 20-3. Start Bit Timing
586
Figure 20-4. Data Bit Timing
586
Table 20-2. Data Bit Timing Parameter Table
586
Figure 20-5. the Process of CEC Line Arbitration
587
Figure 20-6. the Free Time of Signal
587
Table 20-3. the Relationship Betwwen Signal Free Time and Precondition
588
Figure 20-7. Erro Bit Period
589
Figure 20-8. the Timing of Bit Period Long Error
590
Table 20-4. Error Handling Timing Parameter Table
590
Figure 20-9. Transmission Error Detection
591
Table 20-5. TERR Timing Parameter Table
591
Table 20-6. HDMI-CEC Interrupt
592
Figure 21-1. Block Diagram of TSI Module
601
Figure 21-2. Block Diagram of Sample Pin and Channel Pin
602
Table 21-1. Pin and Analog Switch State in a Charge-Transfer Sequence
603
Figure 21-3. Voltage of a Sample Pin During Charge-Transfer Sequence
604
Figure 21-4. FSM Flow of a Charge-Transfer Sequence
605
Table 21-2. Duration Time of Extend Charge State in each Cycle
606
Table 21-3. TSI Errors and Flags
608
Table 21-4. TSI Pins
608
Figure 22-1. USBD Block Diagram
617
Table 22-1. USBD Signal Description
618
Figure 22-2. an Example with Buffer Descriptor Table Usage (USBD_BADDR = 0)
620
Table 22-2. Double-Buffering Buffer Flag Definition
621
Table 22-3. Double Buffer Usage
621
Table 22-4. Reception Status Encoding
633
Table 22-5. Endpoint Type Encoding
634
Table 22-6. Endpoint Kind Meaning
634
Table 22-7. Transmission Status Encoding
634
Figure 23-1. SLCD Block Diagram
638
Figure 23-2. 1/3 Bias, 1/4 Duty
639
Table 23-1. the Odd Frame Voltage
639
Table 23-2. the Even Frame Voltage
640
Table 23-3. the All Common Signal Driver
640
Figure 23-3. 1/4 Bias, 1/6 Duty
641
Figure 23-4. SLCD Dead Time (1/3 Bias, 1/4 Duty)
641
Figure 24-1. OPA0 Signal Route
651
Figure 24-2. OPA1 Signal Route
651
Figure 24-3. OPA2 Signal Route
651
Table 24-1. Operating Mode and Calibration
652
Figure 26-1. CAN Module Block Diagram
664
Figure 26-2. Transmission Register
666
Figure 26-3. State of Transmission Mailbox
667
Figure 26-4. Reception Register
668
Figure 26-5. 32-Bit Filter
669
Figure 26-6. 16-Bit Filter
670
Figure 26-7. 32-Bit Mask Mode Filter
670
Figure 26-8. 16-Bit Mask Mode Filter
670
Figure 26-9. 32-Bit List Mode Filter
670
Figure 26-10. 16-Bit List Mode Filter
670
Table 26-1. 32-Bit Filter Number
671
Table 26-2. Filtering Index
671
Figure 26-11. the Bit Time
674
Figure 26-12. CAN PHY Connection
677
Table 27-1. List of Abbreviations Used in Register
698

GigaDevice Semiconductor GD32F190 Series User Manual (685 pages)

ARM Cortex-M3 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 26.73 MB

Table of Contents
17
Figure 1-1. Cortex™-M3 Block Diagram
28
Figure 1-2. Series System Architecture of Gd32F130Xx and Gd32F150Xx Devices
29
Figure 1-3. Series System Architecture of Gd32F170Xx and Gd32F190Xx Devices
30
Figure 1-5. Memory Map of Gd32F170Xx and Gd32F190Xx Devices
33
Table 1-1. Flash Module Organization
35
Table 1-2. Flash Module Organization
35
Table 1-3. Boot Modes
36
Boot_Mode
38
System Configuration Register 2 (SYSCFG_R2)
43
Figure 2-1. Power Supply Overview of Gd32F130Xx and Gd32F150Xx Devices
48
Figure 2-2. Power Supply Overview of Gd32F170Xx and Gd32F190Xx Devices
49
Figure 2-3. Waveform of the Power Reset
51
Figure 2-4. Waveform of LVD Threshold
52
Table 2-1. Power Saving Mode Summary
54
Table 3-1. Base Address and Size for Flash Memory
60
Figure 3-1. Proccess of Page Erase Operation
62
Figure 3-2. Process of the Mass Erase Operation
63
Figure 3-3. Process of the Word Programming Operation
64
Table 3-4. OB_WP Bit for Pages Protected
67
Address Offset: 0X04 Reset Value: 0X0000
68
This Register Has to be Accessed by Word(32-Bit)
68
Bits Fields
68
Reserved
68
Address Offset: 0X08
68
Reset Value: 0X0000 0000
68
Reserved
70
Must be Kept at Reset Value
70
Figure 4-1. the System Reset Circuit
77
Figure 4-2. Clock Tree of Gd32F130Xx and Gd32F150Xx Devices
78
Figure 4-3. Clock Tree of Gd32F170Xx and Gd32F190Xx Devices
79
Table 4-1. Clock Source Select
83
Table 4-2. Clock Source Select
83
Table 4-3. Core Domain Voltage Selected in Deep-Sleep Mode
84
Table 4-4. Core Domain Voltage Selected in Deep-Sleep Mode
84
Figure 5-1. Basic Structure of a Standard I/O Port Bit
129
Table 5-1. GPIO Configuration Table
129
Figure 5-2. Input Floating/Pull Up/Pull down Configurations
131
Figure 5-3. Output Configuration
132
Figure 5-4. High Impedance-Analog Configuration
132
Figure 5-5. Alternate Function Configuration
133
Figure 6-1.Block Diagram of CRC Calculation Unit
148
Table 7-1. NVIC Exception Types in Cotrex-M3
153
Table 7-2. Interrupt Vector Table of Gd32F130Xx and Gd32F150Xx Devices
153
Figure 7-1. Block Diagram of EXTI
157
Table 7-4. EXTI Source of Gd32F130Xx and Gd32F150Xx Devices
158
Table 7-5. EXTI Source of Gd32F170Xx and Gd32F190Xx Devices
159
Table 8-1. DMA Transfer Operations
165
Table 8-2. DMA Interrupt Event
166
Figure 8-1. DMA Interrupt Generation Logic
167
Figure 8-2. DMA Request Mapping
168
Figure 9-1. Advanced Timer Block Diagram
177
Figure 9-7. Counter Timing Diagram, Internal Clock Divided by N
181
Figure 9-8. Counter Timing Diagram, Update Event When ARSE=0
182
Figure 9-9. Counter Timing Diagram, Update Event When ARSE=1
182
Figure 9-13. Counter Timing Diagram, Internal Clock Divided by N
185
Figure 9-14. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
185
Figure 9-15. Counter Timing Diagram, Internal Clock Divided by 1, Timerx_Carl = 0X5
186
Figure 9-17. Counter Timing Diagram, Internal Clock Divided by 4, Timerx_Carl=0X63
187
Figure 9-18. Counter Timing Diagram, Internal Clock Divided by N
188
Figure 9-19. Counter Timing Diagram, Update Event with ARSE=1(Counter Underflow)
188
Figure 9-20. Counter Timing Diagram, Update Event with ARSE=1 (Counter Overflow)
189
Figure 9-23. Capture/Compare Channel (Example: Channel 1 Input Stage)
192
Figure 9-24. Capture/Compare Channel 1 Main Circuit
193
Figure 9-25. Output Stage of Capture/Compare Channel (Channel 1 to 3)
193
Figure 9-26. Output Stage of Capture/Compare Channel (Channel 4)
193
Figure 9-27. Output Compare Toggle Mode, Toggle on OC1
195
Figure 9-28. Output Compare PWM Mode1 on OC1, Upcounting Mode
195
Figure 9-29. Output Compare PWM Mode1 on OC1, Center-Aligned Counting Mode
196
Figure 9-30. Complementary Output with Dead-Time Insertion
197
Figure 9-31. Dead-Time Waveforms with Delay Greater than the Negative Pulse
197
Figure 9-32. Dead-Time Waveforms with Delay Greater than the Positive Pulse
197
Figure 9-34. Single Pulse Mode
199
Figure 9-35. Example of Counter Operation in Encoder Interface Mode
200
Table 9-1. Counting Direction Versus Encoder Signals
200
Figure 9-36. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
201
Figure 9-37. Control Circuit in Restart Mode
201
Figure 9-38. Control Circuit in Pause Mode
202
Figure 9-39. Control Circuit in Trigger Mode
202
Figure 9-40. Timer1 Master/Slave Mode Timer Example
203
Figure 9-46. General Timer Block Diagram (TIMER2 and TIMER3)
232
Figure 9-52. Counter Timing Diagram, Internal Clock Divided by N
236
Figure 9-53. Counter Timing Diagram, Update Event When ARSE=0
236
Figure 9-54. Counter Timing Diagram, Update Event When ARSE=1
237
Figure 9-58. Counter Timing Diagram, Internal Clock Divided by N
239
Figure 9-59. Counter Timing Diagram, Update Event When Counter Is Not Used
240
Figure 9-60. Counter Timing Diagram, Internal Clock Divided by 1, Timerx_Carl = 0X5
241
Figure 9-62. Counter Timing Diagram, Internal Clock Divided by 4, Timerx_Carl=0X63
242
Figure 9-63. Counter Timing Diagram, Internal Clock Divided by N
242
Figure 9-64. Counter Timing Diagram, Update Event with ARSE=1(Counter Underflow)
243
Figure 9-65. Counter Timing Diagram, Update Event with ARSE=1 (Counter Overflow)
243
Cnt_Clk
243
Cnt_Reg
243
Cnt_Clk
244
Cnt_Reg
244
Figure 9-69. Output Stage of Capture/Compare Channel (Channel 1)
247
Figure 9-70. Output Compare Toggle Mode, Toggle on OC1
248
Figure 9-71. Output Compare PWM Mode1 on OC1, Upcounting Mode
249
Figure 9-72. Output Compare PWM Mode1 on OC1, Center-Aligned Counting Mode
249
Figure 9-74. Example of Counter Operation in Encoder Interface Mode
251
Figure 9-75. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
251
Figure 9-76. Control Circuit in Restart Mode
252
Figure 9-77. Control Circuit in Pause Mode
252
Figure 9-78. Control Circuit in Trigger Mode
253
Figure 9-79. Master/Slave Mode Timer Example
253
Figure 9-80. General Timer Block Diagram (TIMER6)
275
Figure 9-84. General Timer Block Diagram (TIMER14)
283
Figure 9-90. Counter Timing Diagram, Internal Clock Divided by N
287
Figure 9-91. Counter Timing Diagram, Update Event When ARSE=0
287
Figure 9-92. Counter Timing Diagram, Update Event When ARSE=1
288
Figure 9-94. Capture/Compare Channel (Example: Input Stage)
290
Figure 9-95. Capture/Compare Channel 1 Main Circuit
290
Figure 9-96. Output Stage of Capture/Compare Channel
291
Figure 9-97. Output Compare Toggle Mode, Toggle on OC1
292
Figure 9-98. Output Compare PWM Mode1 on OC1, Upcounting Mode
293
Figure 9-99. Output Compare PWM Mode1 on OC1, Center-Aligned Counting Mode
293
Figure 9-100. Gereral Timer Block Diagram (TIMER15)
305
Maybe Used to Implement Input Capture Mode
354
Select Input Signal by Set CCXM Bits in the Channel Control Register (Timerx_Chctlrx)
354
Add Input Filter to Input Signal by Set Chxicf Bitst in the the Channel Control Register (Timerx_Chctlrx)
354
Register (Timerx_Che)
354
If Input Signal Need Prescaler, Set Chxicp Bits in the the Channel Control Register (Timerx_Chctlrx)
354
If Need Interrupt, Set Chxie Bit in DMA and Interrupt Enable Register (Timerx_Die) to
354
If Need DMA Request, Set Chxde Bit in DMA and Interrupt Enable Register (Timerx_Die)
354
Enable the Channel by Set Ccxe Bit in the Channel Enable Register (Timerx_Che) to
354
Table 11-1. Min/Max IWDG Timeout Period at 40 Khz (LSI)
379
Table 11-2. Min-Max Timeout Value at 36 Mhz (Fpclk1)
385
Table 12-4. External Trigger for Regular Channels of ADC
396
Table 12-5. External Trigger for Inserted Channels of ADC
397
Table 12-6. T SAR Timings Depending on Resolution
399
Table 12-7. Maximum Output Results Vs N and M. Grayed Values Indicates Truncation
401
Table 13-1. DAC Pin
417
Table 13-2. External Triggers of DAC
420
Table 14-1. Definition of I2C-Bus Terminology
434
Table 14-2. Event Status Flags
449
Table 14-3. I2C Error Flags
449
Table 15-2. I2S Bitrate Calculation Formulas
481
Table 15-3. Audio Sampling Frequency Calculation Formulas
482
Table 15-4. Audio Sampling Frequency Configuration and Precision
482
Table 15-5. Direction of I2S Interface Signals for each Operation Mode
483
Table 15-6. I2S Interrupt
484
Table 17-1. USART Important Pins Description
509
Table 17-2. Stop Bits Configuration
511
Table 17-3. USART Interrupt Requests
521
Table 19-1. Gd32F150Xx USB Implementation
549
Table 19-2. Gd32F150Xx USB Signal Pinouts
550
Table 19-3. Double-Buffering Buffer Flag Definition
555
Table 19-9. Sub-Endpoints Status
570
Table 21-1. Pin and Analog Switch State in a Charge-Transfer Sequence
604
Table 21-2. Duration Time of Extend Charge State in each Cycle
607
Table 21-4. TSI Pins
609
Table 22-2. Error Handling Timing Parameter Table
622
Table 22-3. te Timing Parameter Table
623
Table 23-1. the Odd Frame Voltage
634

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