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GigaDevice Semiconductor GD32F30 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32F30 Series. We have
1
GigaDevice Semiconductor GD32F30 Series manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32F30 Series User Manual (883 pages)
Arm Cortex-M4 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 10.97 MB
Table of Contents
Table of Contents
2
Gd32F30X User Manual List of Figures
19
List of Figures
19
List of Table
26
Arm ® Cortex ® -M4 Processor
30
System and Memory Architecture
30
Figure 1-1. the Structure of the Cortex
31
System Architecture
31
Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix
31
Figure 1-2. GD32F303 Series System Architecture
33
Figure 1-3. GD32F305 and GD32F307 Series System Architecture
34
Memory Map
34
Table 1-2. Memory Map of Gd32F30X Devices
35
Bit-Banding
38
Boot Configuration
39
On-Chip Flash Memory Overview
39
On-Chip SRAM Memory
39
Table 1-3. Boot Modes
39
Device Electronic Signature
40
Table 1-4. Bootloader Supported Peripherals
40
Memory Density Information
41
Unique Device ID (96 Bits)
41
System Configuration Registers
42
Flash Memory Architecture
43
Flash Memory Controller (FMC)
43
Function Description
43
Introduction
43
Main Features
43
Table 2-1. Gd32F30X_Cl and Gd32F30X_Hd, Gd32F30X_Xd Base Address and Size for Flash
43
Read Operations
44
Unlock the Fmc_Ctlx Registers
44
Figure 2-1. Process of Page Erase Operation
45
Page Erase
45
Mass Erase
46
Figure 2-2. Process of Mass Erase Operation
47
Main Flash Programming
48
Figure 2-3. Process of Word Program Operation
49
Option Bytes Erase
49
Option Bytes Description
50
Option Bytes Modify
50
Table 2-2. Option Byte
50
Page Erase/Program Protection
51
Security Protection
52
FMC Registers
53
Unlock Key Register 0(FMC_KEY0)
53
Wait State Register (FMC_WS)
53
Option Byte Unlock Key Register (FMC_OBKEY)
54
Status Register 0 (FMC_STAT0)
54
Control Register 0(FMC_CTL0)
55
Address Register 0 (FMC_ADDR0)
56
Erase/Program Protection Register (FMC_WP)
57
Option Byte Status Register (FMC_OBSTAT)
57
Status Register 1 (FMC_STAT1)
58
Unlock Key Register 1(FMC_KEY1)
58
Control Register 1(FMC_CTL1)
59
Address Register 1 (FMC_ADDR1)
60
Wait State Enable Register (FMC_WSEN)
60
Product ID Register (FMC_PID)
61
Characteristics
62
Figure 3-1. Power Supply Overview
62
Function Overview
62
Overview
62
Power Management Unit (PMU)
62
Backup Domain
63
Figure 3-2. Waveform of the por / PDR
64
VDD
64
Figure 3-3. Waveform of the LVD Threshold
65
Power Domain
66
Power Saving Modes
66
Table 3-1. Power Saving Mode Summary
68
Control Register (PMU_CTL)
70
PMU Registers
70
Control and Status Register (PMU_CS)
72
Backup Registers (BKP)
74
Function Description
74
Introduction
74
Main Features
74
RTC Clock Calibration
74
Tamper Detection
74
Backup Data Register X (Bkp_Datax) (X= 0
76
BKP Registers
76
RTC Signal Output Control Register (BKP_OCTL)
76
Tamper Control and Status Register (BKP_TPCS)
77
Tamper Pin Control Register (BKP_TPCTL)
77
Function Overview
79
High- and Extra-Density Eset and Clock Control Unit (RCU)
79
Overview
79
Reset and Clock Unit (RCU)
79
Reset Control Unit (RCTL)
79
Clock Control Unit (CCTL)
80
Figure 5-1. the System Reset Circuit
80
Overview
80
Figure 5-2. Clock Tree
81
Characteristics
82
Figure 5-3. HXTAL Clock Source
82
Function Overview
82
Figure 5-4. HXTAL Clock Source in Bypass Mode
83
Table 5-1. Clock Output 0 Source Select
85
Table 5-2. 1.2V Domain Voltage Selected in Deep-Sleep Mode
85
Control Register (RCU_CTL)
86
Register Definition
86
Clock Configuration Register 0 (RCU_CFG0)
87
Clock Interrupt Register (RCU_INT)
91
APB2 Reset Register (RCU_APB2RST)
94
APB1 Reset Register (RCU_APB1RST)
96
AHB Enable Register (RCU_AHBEN)
99
APB2 Enable Register (RCU_APB2EN)
100
APB1 Enable Register (RCU_APB1EN)
102
Backup Domain Control Register (RCU_BDCTL)
105
Reset Source/Clock Register (RCU_RSTSCK)
107
Clock Configuration Register 1 (RCU_CFG1)
108
Deep-Sleep Mode Voltage Register (RCU_DSV)
109
Additional Clock Control Register (RCU_ADDCTL)
110
Additional Clock Interrupt Register (RCU_ADDINT)
110
APB1 Additional Reset Register (RCU_ADDAPB1RST)
111
APB1 Additional Enable Register (RCU_ADDAPB1EN)
112
Connectivity Line Devices: Reset and Clock Control Unit (RCU)
113
Function Overview
113
Overview
113
Reset Control Unit (RCTL)
113
Clock Control Unit (CCTL)
114
Figure 5-4. the System Reset Circuit
114
Overview
114
Figure 5-5. Clock Tree
115
Characteristics
116
Function Overview
116
Figure 5-4. HXTAL Clock Source in Bypass Mode
117
Figure 5-6. HXTAL Clock Source
117
Table 5-3. Clock Output 0 Source Select
120
Table 5-4. 1.2V Domain Voltage Selected in Deep-Sleep Mode
120
Control Register (RCU_CTL)
121
Register Definition
121
Clock Configuration Register 0 (RCU_CFG0)
123
Clock Interrupt Register (RCU_INT)
126
APB2 Reset Register (RCU_APB2RST)
130
APB1 Reset Register (RCU_APB1RST)
132
AHB Enable Register (RCU_AHBEN)
135
APB2 Enable Register (RCU_APB2EN)
136
APB1 Enable Register (RCU_APB1EN)
139
Backup Domain Control Register (RCU_BDCTL)
142
Reset Source/Clock Register (RCU_RSTSCK)
143
AHB Reset Register (RCU_AHBRST)
145
Clock Configuration Register 1 (RCU_CFG1)
145
Deep-Sleep Mode Voltage Register (RCU_DSV)
148
Additional Clock Control Register (RCU_ADDCTL)
149
Additional Clock Interrupt Register (RCU_ADDINT)
150
APB1 Additional Reset Register (RCU_ADDAPB1RST)
150
APB1 Additional Enable Register (RCU_ADDAPB1EN)
151
Characteristics
152
Clock Trim Controller (CTC)
152
Figure 6-1. CTC Overview
152
Function Overview
152
Overview
152
CTC Trim Counter
153
REF Sync Pulse Generator
153
Figure 6-2. CTC Trim Counter
154
Frequency Evaluation and Automatically Trim Process
154
Software Program Guide
155
Control Register 0 (CTC_CTL0)
157
Register Definition
157
Control Register 1 (CTC_CTL1)
158
Status Register (CTC_STAT)
159
Interrupt Clear Register (CTC_INTC)
161
Characteristics
163
Interrupt / Event Controller (EXTI)
163
Interrupts Function Overview
163
Overview
163
Table 7-1. NVIC Exception Types in Cortex ® -M4
164
Table 7-2. Interrupt Vector Table
164
External Interrupt and Event (EXTI) Block Diagram
167
External Interrupt and Event Function Overview
167
Figure 7-1. Block Diagram of EXTI
167
Table 7-3. EXTI Source
168
Event Enable Register (EXTI_EVEN)
170
EXTI Register
170
Interrupt Enable Register (EXTI_INTEN)
170
Falling Edge Trigger Enable Register (EXTI_FTEN)
171
Rising Edge Trigger Enable Register (EXTI_RTEN)
171
Software Interrupt Event Register (EXTI_SWIEV)
171
Pending Register (EXTI_PD)
172
Characteristics
173
Function Overview
173
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
173
Overview
173
Table 8-1. GPIO Configuration Table
173
Figure 8-1. Basic Structure of a Standard I/O Port Bit
174
GPIO Pin Configuration
174
Alternate Functions (AF)
175
External Interrupt/Event Lines
175
Figure 8-2. Input Configuration
175
Input Configuration
175
Figure 8-3. Output Configuration
176
Output Configuration
176
Alternate Function (AF) Configuration
177
Analog Configuration
177
Figure 8-4. Analog Configuration
177
Figure 8-5. Alternate Function Configuration
177
GPIO I/O Compensation Cell
178
GPIO Locking Function
178
Introduction
178
Remapping Function I/O and Debug Configuration
178
JTAG/SWD Alternate Function Remapping
179
Main Features
179
Table 8-2. Debug Interface Signals
179
Table 8-3. Debug Port Mapping and Pin Availability
179
ADC AF Remapping
180
Table 8-4. ADC0/ADC1 External Trigger Rountine Conversion AF Remapping
180
Table 8-5. Timerx Alternate Function Remapping
180
TIMER AF Remapping
180
Table 8-6. TIMER4 Alternate Function Remapping
181
I2C0 AF Remapping
182
Table 8-7. USART Alternate Function Remapping
182
USART AF Remapping
182
CAN AF Remapping
183
SPI/I2S AF Remapping
183
Table 8-10. CAN Alternate Function Remapping
183
Table 8-8. I2C0 Alternate Function Remapping
183
Table 8-9. SPI/I2S Alternate Function Remapping
183
CLK Pins AF Remapping
184
CTC AF Remapping
184
Ethernet AF Remapping
184
Table 8-11. ENET Alternate Function Remapping
184
Table 8-12. CTC Alternate Function Remapping
184
Table 8-13. OSC32 Pins Configuration
185
Table 8-14. OSC Pins Configuration
185
Port Control Register 0 (Gpiox_Ctl0, X=A
186
Register Definition
186
Port Control Register 1 (Gpiox_Ctl1, X=A
188
Port Input Status Register (Gpiox_Istat, X=A
189
Port Bit Operate Register (Gpiox_Bop , X=A
190
Port Output Control Register (Gpiox_Octl, X=A
190
Port Bit Clear Register (Gpiox_Bc, X=A
191
Port Configuration Lock Register (Gpiox_Lock, X=A
191
Port Bit Speed Register (Gpiox_ SPD, X=A
192
AFIO Port Configuration Register 0 (AFIO_PCF0)
193
Event Control Register (AFIO_EC)
193
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
200
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
202
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
203
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
204
AFIO Port Configuration Register 1 (AFIO_PCF1)
205
IO Compensation Control Register (AFIO_CPSCTL)
207
Characteristics
208
Cyclic Redundancy Checks Management Unit (CRC)
208
Overview
208
Figure 9-1. Block Diagram of CRC Calculation Unit
209
Function Overview
209
Data Register (CRC_DATA)
210
Free Data Register (CRC_FDATA)
210
Register Definition
210
Control Register (CRC_CTL)
211
Characteristics
212
Direct Memory Access Controller (DMA)
212
Overview
212
Block Diagram
213
DMA Operation
213
Figure 10-1. Block Diagram of DMA
213
Function Overview
213
Table 10-1. DMA Transfer Operation
214
Address Generation
215
Arbitration
215
Figure 10-2. Handshake Mechanism
215
Peripheral Handshake
215
Channel Configuration
216
Circular Mode
216
Interrupt
216
Memory to Memory Mode
216
DMA Request Mapping
217
Figure 10-3. DMA Interrupt Logic
217
Table 10-2. Interrupt Events
217
Table 10-3. DMA0 Requests for each Channel
217
Table 10-4. DMA1 Requests for each Channel
217
Figure 10-4. DMA0 Request Mapping
218
Figure 10-5. DMA1 Request Mapping
219
Interrupt Flag Register (DMA_INTF)
221
Register Definition
221
Channel X Control Register (Dma_Chxctl)
222
Interrupt Flag Clear Register (DMA_INTC)
222
Channel X Counter Register (Dma_Chxcnt)
224
Channel X Memory Base Address Register (Dma_Chxmaddr)
225
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
225
Debug (DBG)
227
Introduction
227
JTAG/SW Function Description
227
Pin Assignment
227
Switch JTAG or SW Interface
227
Debug Hold Function Description
228
Debug Reset
228
Debug Support for Power Saving Mode
228
JEDEC-106 ID Code
228
JTAG Daisy Chained Structure
228
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
229
Control Register 0 (DBG_CTL0)
230
DBG Registers
230
ID Code Register (DBG_ID)
230
Analog-To-Digital Converter (ADC)
234
Characteristics
234
Overview
234
Figure 12-1. ADC Module Block Diagram
235
Pins and Internal Signals
235
Table 12-1. ADC Internal Input Signals
235
Table 12-2. ADC Input Pins Definition
235
Foreground Calibration Function
236
Functional Overview
236
ADC Clock
237
ADC Enable
237
Figure 12-2. Single Operation Mode
237
Operation Modes
237
Routine Sequence
237
Figure 12-3. Continuous Operation Mode
238
Figure 12-4. Scan Operation Mode, Continuous Disable
239
Figure 12-5. Scan Operation Mode, Continuous Enable
239
Conversion Result Threshold Monitor Function
240
Data Storage Mode
240
Figure 12-6. Discontinuous Operation Mode
240
External Trigger Configuration
241
Figure 12-10. 6-Bit Data Storage Mode
241
Figure 12-9. 12-Bit Data Storage Mode
241
Sample Time Configuration
241
Table 12-3. External Trigger Source for ADC0 and ADC1
241
ADC Internal Channels
242
DMA Request
242
Table 12-4. External Trigger Source for ADC2
242
On-Chip Hardware Oversampling
243
Programmable Resolution (DRES)
243
Table 12-5. Tconv Timings Depending on Resolution
243
Figure 12-11. 20-Bit to 16-Bit Result Truncation
244
Figure 12-12. Numerical Example with 5-Bits Shift and Rounding
244
Table 12-6. Maximum Output Results Vs N and M Grayed Values Indicates Truncation
244
ADC Sync Mode
245
Table 12-7. ADC Sync Mode Table
245
Figure 12-13. ADC Sync Block Diagram
246
Free Mode
246
Routine Parallel Mode
246
Figure 12-14. Routine Parallel Mode on 10 Channels
247
Figure 12-16. Routine Follow-Up Fast Mode (the CTN Bit of Adcs Are Set)
247
Routine Follow-Up Fast Mode
247
Routine Follow-Up Slow Mode
247
ADC Interrupts
248
Figure 12-17. Routine Follow-Up Slow Mode
248
ADC Registers
249
Status Register (ADC_STAT)
249
Control Register 0 (ADC_CTL0)
250
Control Register 1 (ADC_CTL1)
251
Sample Time Register 0 (ADC_SAMPT0)
253
Sample Time Register 1 (ADC_SAMPT1)
254
Watchdog High Threshold Register (ADC_WDHT)
255
Watchdog Low Threshold Register (ADC_WDLT)
255
Routine Sequence Register 0 (ADC_RSQ0)
256
Routine Sequence Register 1 (ADC_RSQ1)
256
Routine Sequence Register 2 (ADC_RSQ2)
257
Oversample Control Register (ADC_OVSAMPCTL)
258
Routine Data Register (ADC_RDATA)
258
Characteristics
261
Digital-To-Analog Converter (DAC)
261
Figure 13-1. DAC Block Diagram
261
Introduction
261
DAC Enable
262
DAC Output Buffer
262
Function Description
262
Table 13-1. DAC I/O Description
262
DAC Data Configuration
263
DAC Noise Wave
263
DAC Trigger
263
DAC Workflow
263
Table 13-2. External Triggers of DAC
263
DAC Output Calculate
264
Figure 13-2. DAC LFSR Algorithm
264
Figure 13-3. DAC Triangle Noise Wave
264
DAC Concurrent Conversion
265
DMA Function
265
Control Register (DAC_CTL)
266
DAC Registers
266
Software Trigger Register (DAC_SWT)
268
DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12DH)
269
DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12DH)
269
DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8DH)
270
DAC1 12-Bit Right-Aligned Data Holding Register (DAC1_R12DH)
270
DAC1 12-Bit Left-Aligned Data Holding Register (DAC1_L12DH)
271
DAC1 8-Bit Right-Aligned Data Holding Register (DAC1_R8DH)
271
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
272
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
272
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
273
DAC0 Data Output Register (DAC0_DO)
273
DAC1 Data Output Register (DAC1_DO)
274
Characteristics
275
Free Watchdog Timer (FWDGT)
275
Function Overview
275
Overview
275
Watchdog Timer (WDGT)
275
Figure 14-1. Free Watchdog Block Diagram
276
Table 14-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
276
Register Definition
278
Characteristics
281
Figure 14-2. Window Watchdog Timer Block Diagram
281
Function Overview
281
Overview
281
Window Watchdog Timer (WWDGT)
281
Figure 14-3. Window Watchdog Timing Diagram
282
Table 14-2. Min/Max Timeout Value at 60 Mhz
283
Register Definition
284
Characteristics
286
Function Overview
286
Overview
286
Real-Time Clock(RTC)
286
Figure 15-1. Block Diagram of RTC
287
RTC Configuration
287
RTC Reading
287
RTC Reset
287
RTC Flag Assertion
288
RTC Control Register(RTC_CTL)
290
RTC Interrupt Enable Register(RTC_INTEN)
290
RTC Register
290
RTC Prescaler High Register (RTC_PSCH)
291
RTC Divider High Register (RTC_DIVH)
292
RTC Divider Low Register (RTC_DIVL)
292
RTC Prescaler Low Register(RTC_PSCL)
292
RTC Counter High Register(RTC_CNTH)
293
RTC Counter Low Register (RTC_CNTL)
293
RTC Alarm High Register(RTC_ALRMH)
294
RTC Alarm Low Register (RTC_ALRML)
294
Table 16-1. Timers (Timerx) Are Divided into Five Sorts
295
Timer(Timerx)
295
Advanced Timer (Timerx, X=0, 7)
296
Characteristics
296
Overview
296
Block Diagram
297
Figure 16-1. Advanced Timer Block Diagram
297
Figure 16-2. Timing Chart of Internal Clock Divided by 1
298
Function Overview
298
Figure 16-3. Timing Chart of PSC Value Change from 0 to 2
299
Figure 16-4. Timing Chart of up Counting Mode, PSC=0/2
300
Figure 16-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
301
Figure 16-6. Timing Chart of down Counting Mode, PSC=0/2
301
Figure 16-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
303
Figure 16-8. Center-Aligned Counter Timechart
303
Figure 16-10. Repetition Timechart for Up-Counter
305
Figure 16-9. Repetition Timechart for Center-Aligned Counter
305
Figure 16-11. Repetition Timechart for Down-Counter
306
Figure 16-12. Channel Input Capture Principle
307
Figure 16-13. Output-Compare under Three Modes
309
Figure 16-14. EAPWM Timechart
309
Figure 16-15. CAPWM Timechart
309
Table 16-2. Complementary Outputs Controlled by Parameters
312
Figure 16-16. Complementary Output with Dead-Time Insertion
313
Figure 16-17. Output Behavior in Response to a Break(the Break High Active)
314
Figure 16-18. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
315
Figure 16-19. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
315
Table 16-3. Counting Direction in Different Quadrature Decoder Mode
315
Figure 16-20. Hall Sensor Is Used to BLDC Motor
316
Figure 16-21. Hall Sensor Timing between Two Timers
317
Figure 16-22. Restart Mode
318
Table 16-4. Examples of Slave Mode
318
Figure 16-23. Pause Mode
319
Figure 16-24. Event Mode
319
Figure 16-25. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
320
Figure 16-26. Timer0 Master/Slave Mode Timer Example
320
Figure 16-27. Triggering TIMER0 with Enable Signal of TIMER2
322
Figure 16-28. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input
323
Timerx Registers(X=0, 7)
324
Block Diagram
350
Characteristics
350
Figure 16-29. General Level 0 Timer Block Diagram
350
General Level0 Timer (Timerx, X=1, 2, 3, 4)
350
Overview
350
Figure 16-30. Timing Chart of Internal Clock Divided by 1
352
Function Overview
352
Figure 16-31. Timing Chart of PSC Value Change from 0 to 2
353
Figure 16-32. Timing Chart of up Counting Mode, PSC=0/2
354
Figure 16-33. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
355
Figure 16-34. Timing Chart of down Counting Mode, PSC=0/2
355
Figure 16-35. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
356
Figure 16-36. Timing Chart of Center-Aligned Counting Mode
357
Figure 16-37. Channel Input Capture Principle
359
Figure 16-38. Output-Compare under Three Modes
361
Figure 16-39. EAPWM Timechart
361
Figure 16-40. CAPWM Timechart
361
Table 16-5. Examples of Slave Mode
363
Figure 16-41. Restart Mode
364
Figure 16-42. Pause Mode
364
Figure 16-43. Event Mode
365
Timerx Registers(X=1, 2, 3, 4)
367
Characteristics
388
General Level1 Timer (Timerx, X=8, 11)
388
Overview
388
Block Diagram
389
Figure 16-44. General Level1 Timer Block Diagram
389
Figure 16-45. Timing Chart of Internal Clock Divided by 1
390
Function Overview
390
Figure 16-46. Timing Chart of PSC Value Change from 0 to 2
391
Figure 16-47. Timing Chart of up Counting Mode, PSC=0/2
392
Figure 16-48. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
392
Figure 16-49. Channel Input Capture Principle
393
Figure 16-50. Output-Compare under Three Modes
395
Figure 16-51. EAPWM Timechart
396
Figure 16-52. CAPWM Timechart
396
Table 16-6.Examples of Slave Mode
397
Figure 16-53. Restart Mode
398
Figure 16-54. Pause Mode
398
Figure 16-55. Event Mode
399
Figure 16-56. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
399
Timerx Registers(X=8, 11)
401
Block Diagram
413
Characteristics
413
Figure 16-57. General Level2 Timer Block Diagram
413
General Level2 Timer (Timerx, X=9, 10, 12, 13)
413
Overview
413
Figure 16-58. Timing Chart of Internal Clock Divided by 1
415
Function Overview
415
Figure 16-59. Timing Chart of PSC Value Change from 0 to 2
416
Figure 16-60. Timing Chart of up Counting Mode, PSC=0/2
417
Figure 16-61. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
417
Figure 16-62. Channel Input Capture Principle
418
Figure 16-63. Output-Compare under Three Modes
420
Timerx Registers(X=9, 10, 12, 13)
422
Basic Timer (Timerx, X=5, 6)
432
Block Diagram
432
Characteristics
432
Figure 16-64. Basic Timer Block Diagram
432
Function Overview
432
Overview
432
Figure 16-65. Timing Chart of Internal Clock Divided by 1
433
Figure 16-66. Timing Chart of PSC Value Change from 0 to 2
433
Figure 16-67. Timing Chart of up Counting Mode, PSC=0/2
434
Figure 16-68. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
435
Table 17-1. Description of USART Important Pins
442
Figure 17-1. USART Module Block Diagram
443
Figure 17-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
443
Table 17-2. Configuration of Stop Bits
443
Figure 17-3. USART Transmit Procedure
445
Figure 17-4. Receiving a Frame Bit by Oversampling Method
446
Figure 17-5. Configuration Step When Using DMA for USART Transmission
447
Figure 17-6. Configuration Steps When Using DMA for USART Reception
448
Figure 17-7. Hardware Flow Control between Two Usarts
449
Figure 17-8. Hardware Flow Control
449
Figure 17-10. Break Frame Occurs During a Frame
451
Figure 17-11. Example of USART in Synchronous Mode
451
Figure 17-9. Break Frame Occurs During Idle State
451
Figure 17-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
452
Figure 17-13. Irda SIR ENDEC Module
452
Figure 17-14. Irda Data Modulation
453
Figure 17-15. ISO7816-3 Frame Format
454
Figure 17-16. USART Interrupt Mapping Diagram
456
Table 17-3. USART Interrupt Requests
456
Figure 18-1. I2C Module Block Diagram
470
Table 18-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
471
Figure 18-2. Data Validation
472
Figure 18-3. START and STOP Condition
472
Figure 18-4. Clock Synchronization
473
Figure 18-5. SDA Line Arbitration
473
Figure 18-6. I2C Communication Flow with 7-Bit Address
474
Figure 18-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
474
Figure 18-8. I2C Communication Flow with 10-Bit Address (Master Receive)
474
Figure 18-10. Programming Model for Slave Receiving (10-Bit Address Mode)
476
Figure 18-9. Programming Model for Slave Transmitting Mode (10-Bit Address Mode)
476
Figure 18-11. Programming Model for Master Transmitting Mode (10-Bit Address Mode)
477
Figure 18-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)
480
Figure 18-13. Programming Model for Master Receiving Mode Using Solution B
482
Table18-2. Event Status Flags
486
Table18-3. I2C Error Flags
486
Figure 19-1. Block Diagram of SPI
500
Table 19-1. SPI Signal Description
500
Figure 19-2. SPI Timing Diagram in Normal Mode
501
Table 19-2. Quad-SPI Signal Description
501
Figure 19-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
502
Table 19-3. NSS Function in Slave Mode
502
Table 19-4. NSS Function in Master Mode
503
Table 19-5. SPI Operation Modes
503
Figure 19-4. a Typical Full-Duplex Connection
505
Figure 19-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
505
Figure 19-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
505
Figure 19-7. a Typical Bidirectional Connection
505
Figure 19-8. Timing Diagram of TI Master Mode with Discontinuous Transfer
507
Figure 19-10. Timing Diagram of TI Slave Mode
508
Figure 19-9. Timing Diagram of TI Master Mode with Continuous Transfer
508
Figure 19-11. Timing Diagram of NSS Pulse with Continuous Transmit
509
Figure 19-12. Timing Diagram of Quad Write Operation in Quad-SPI Mode
510
Figure 19-13. Timing Diagram of Quad Read Operation in Quad-SPI Mode
511
Table 19-6. SPI Interrupt Requests
513
Figure 19-14. Block Diagram of I2S
514
Figure 19-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
515
Figure 19-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
515
Figure 19-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
516
Figure 19-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
516
Figure 19-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
516
Figure 19-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
516
Figure 19-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
517
Figure 19-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
517
Figure 19-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
517
Figure 19-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
517
Figure 19-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
517
Figure 19-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
518
Figure 19-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
518
Figure 19-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
518
Figure 19-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
518
Figure 19-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
518
Figure 19-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
519
Figure 19-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
519
Figure 19-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
519
Figure 19-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
519
Figure 19-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
520
Figure 19-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
520
Figure 19-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
520
Figure 19-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
520
Figure 19-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
520
Figure 19-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
521
Figure 19-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
521
Figure 19-43. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
521
Figure 19-45. PCM Standard Long Frame Synchronization Mode Timing Diagram
521
Figure19-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
521
Figure19-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
521
Figure 19-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
522
Figure 19-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
522
Figure 19-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
522
Figure 19-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
522
Figure 19-50. PCM Standard Long Frame Synchronization Mode Timing Diagram
522
Figure 19-51. Block Diagram of I2S Clock Generator
523
Table 19-7. I2S Bitrate Calculation Formulas
523
Figure 19-52. I2S Initialization Sequence
524
Table 19-8. Audio Sampling Frequency Calculation Formulas
524
Table 19-9. Direction of I2S Interface Signals for each Operation Mode
524
Figure 19-53. I2S Master Reception Disabling Sequence
527
Table 19-10. I2S Interrupt
529
Figure 20-1. SDIO "No Response" and "No Data" Operations
542
Figure 20-2. SDIO Multiple Blocks Read Operation
542
Figure 20-3. SDIO Multiple Blocks Write Operation
542
Figure 20-4. SDIO Sequential Read Operation
542
Figure 20-5. SDIO Sequential Write Operation
543
Figure 20-6. SDIO Block Diagram
544
Table 20-1. SDIO I/O Definitions
545
Figure 20-7. Command Token Format
551
Table 20-2. Command Format
551
Table 20-3. Card Command Classes (Cccs)
552
Table 20-4. Basic Commands (Class 0)
554
Table 20-5. Block-Oriented Read Commands (Class 2)
555
Table 20-6. Stream Read Commands (Class 1) and Stream Write Commands (Class 3)
556
Table 20-7. Block-Oriented Write Commands (Class 4)
556
Table 20-8. Erase Commands (Class 5)
557
Table 20-9. Block Oriented Write Protection Commands (Class 6)
558
Table 20-10. Lock Card (Class 7)
559
Table 20-11. Application-Specific Commands (Class 8)
559
Table 20-12. I/O Mode Commands (Class 9)
560
Table 20-13. Switch Function Commands (Class 10)
561
Figure 20-8. Response Token Format
562
Table 20-14. Response R1
563
Table 20-15. Response R2
563
Table 20-16. Response R3
564
Table 20-17. Response R4 for MMC
564
Table 20-18. Response R4 for SD I/O
564
Table 20-19. Response R5 for MMC
564
Table 20-20. Response R5 for SD I/O
565
Table 20-21. Response R6
565
Table 20-22. Response R7
565
Figure 20-10. 4-Bit Data Bus Width
566
Figure 20-11. 8-Bit Data Bus Width
566
Figure 20-9. 1-Bit Data Bus Width
566
Table 20-23. Card Status
567
Table 20-24. SD Status
570
Table 20-25. Performance Move Field
572
Table 20-26. AU_SIZE Field
572
Table 20-27. Maximum au Size
572
Table 20-28. Erase Size Field
573
Table 20-29. Erase Timeout Field
573
Table 20-30. Erase Offset Field
573
Table 20-31. Lock Card Data Structure
582
Figure 20-12. Read Wait Control by Stopping SDIO_CLK
584
Figure 20-13. Read Wait Operation Using SDIO_DAT[2]
585
Figure 20-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle
585
Figure 20-15. Read Interrupt Cycle Timing
586
Figure 20-16. Write Interrupt Cycle Timing
587
Figure 20-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
587
Figure 20-18. Multiple Block 4-Bit Write Interrupt Cycle Timing
587
Figure 20-19. the Operation for Command Completion Disable Signal
588
Table 20-32. Sdio_Respx Register at Different Response Type
593
Figure 21-1. the EXMC Block Diagram
604
Figure 21-2. EXMC Memory Banks
605
Figure 21-3. Four Regions of Bank0 Address Mapping
605
Figure 21-4. NAND/PC Card Address Mapping
607
Figure 21-5. Diagram of Bank1 Common Space
607
Table 21-1. nor Flash Interface Signals Description
608
Table 21-2. PSRAM Non-Muxed Signal Description
609
Table 21-3. EXMC Bank 0 Supports All Transactions
609
Table 21-4. nor / PSRAM Controller Timing Parameters
610
Table 21-5. Exmc_Timing Models
611
Figure 21-6. Mode 1 Read Access
612
Figure 21-7. Mode 1 Write Access
612
Table 21-6. Mode 1 Related Registers Configuration
612
Figure 21-8. Mode a Read Access
613
Figure 21-9. Mode a Write Access
614
Table 21-7. Mode a Related Registers Configuration
614
Figure 21-10. Mode 2/B Read Access
615
Figure 21-11. Mode 2 Write Access
616
Figure 21-12. Mode B Write Access
616
Table 21-8. Mode 2/B Related Registers Configuration
616
Figure 21-13. Mode C Read Access
617
Figure 21-14. Mode C Write Access
618
Table 21-9. Mode C Related Registers Configuration
618
Figure 21-15. Mode D Read Access
619
Figure 21-16. Mode D Write Access
620
Table 21-10. Mode D Related Registers Configuration
620
Figure 21-17. Multiplex Mode Read Access
621
Figure 21-18. Multiplex Mode Write Access
621
Table 21-11. Multiplex Mode Related Registers Configuration
622
Figure 21-19. Read Access Timing Diagram under Async-Wait Signal Assertion
623
Figure 21-20. Write Access Timing Diagram under Async-Wait Signal Assertion
623
Figure 21-21. Read Timing of Synchronous Multiplexed Burst Mode
625
Table 21-12. Timing Configurations of Synchronous Multiplexed Read Mode
625
Figure 21-22. Write Timing of Synchronous Multiplexed Burst Mode
626
Table 21-13. Timing Configurations of Synchronous Multiplexed Write Mode
626
Table 21-14. 8-Bit or 16-Bit NAND Interface Signal
627
Table 21-15. 16-Bit PC Card Interface Signal
628
Table 21-16. Bank1/2/3 of EXMC Support the Memory and Access Mode
628
Figure 21-23. Access Timing of Common Memory Space of PC Card Controller
629
Table 21-17. NAND Flash or PC Card Programmable Parameters
629
Figure 21-24. Access to None "NCE Don't Care" NAND Flash
630
Figure 22-1. CAN Module Block Diagram
645
Figure 22-2. Transmission Register
647
Figure 22-3. State of Transmit Mailbox
648
Figure 22-4. Reception Register
649
Figure 22-10. 16-Bit List Mode Filter
651
Figure 22-5. 32-Bit Filter
651
Figure 22-6. 16-Bit Filter
651
Figure 22-7. 32-Bit Mask Mode Filter
651
Figure 22-8. 16-Bit Mask Mode Filter
651
Figure 22-9. 32-Bit List Mode Filter
651
Table 22-1. 32-Bit Filter Number
652
Table 22-2. Filtering Index
653
Figure 22-11. the Bit Time
655
Table 22-3. CAN Event / Interrupt Flags
657
Figure 23-1. ENET Module Block Diagram
680
Figure 23-2. Mac/Tagged MAC Frame Format
681
Table 23-1. Ethernet Signals (MII Default)
682
Table 23-2. Ethernet Signals (MII Remap)
682
Table 23-3. Ethernet Signals (RMII Default)
683
Table 23-4. Ethernet Signals (RMII Remap)
683
Figure 23-3. Station Management Interface Signals
684
Table 23-5. Clock Range
685
Figure 23-4. Media Independent Interface Signals
686
Table 23-6. Rx Interface Signal Encoding
687
Figure 23-5. Reduced Media-Independent Interface Signals
688
Table 23-7. Destination Address Filtering Table
693
Table 23-8. Source Address Filtering Table
693
Figure 23-6. Descriptor Ring and Chain Structure
701
Figure 23-7. Transmit Descriptor in Normal Mode
706
Figure 23-8. Transmit Descriptor in Enhanced Mode
712
Figure 23-9. Receive Descriptor in Normal Mode
716
Table 23-9. Error Status Decoding in Receive Descriptor0, Only Used for Normal Descriptor (DFM=0)
719
Figure 23-10. Receive Descriptor in Enhanced Mode
722
Figure 23-11. Wakeup Frame Filter Register
727
Figure 23-12. System Time Update Using the Fine Correction Method
729
Figure 23-13. MAC Interrupt Scheme
734
Figure 23-14. Ethernet Interrupt Scheme
735
Figure 23-15. Wakeup Frame Filter Register
745
Table 23-10. Supported Time Stamp Snapshot with PTP Register Configuration
764
Figure 24-1. USBD Block Diagram
786
Table 24-1. USBD Signal Description
787
Figure 24-2. an Example with Buffer Descriptor Table Usage (USBD_BADDR = 0)
789
Table 24-2. Double-Buffering Buffer Flag Definition
790
Table 24-3. Double Buffer Usage
790
Table 24-4. Reception Status Encoding
802
Table 24-5. Endpoint Type Encoding
803
Table 24-6. Endpoint Kind Meaning
803
Table 24-7. Transmission Status Encoding
803
Figure 25-1. USBFS Block Diagram
807
Table 25-1. USBFS Signal Description
807
Figure 25-2. Connection with Host or Device Mode
808
Figure 25-3. Connection with OTG Mode
809
Figure 25-4. State Transition Diagram of Host Port
809
Figure 25-5. HOST Mode FIFO Space in SRAM
814
Figure 25-6. Host Mode FIFO Access Register Map
814
Figure 25-7. Device Mode FIFO Space in SRAM
815
Figure 25-8. Device Mode FIFO Access Register Map
815
Table 25-2. USBFS Global Interrupt
820
Table 26-1. Revision History
880
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