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GigaDevice Semiconductor GD32F20 Series User Manual

Arm cortex-m3 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32F20x

™

®

ARM

Cortex

-M3 32-bit MCU

User Manual

Revision 2.2

( Oct. 2019 )

Table of Contents

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Summary of Contents for GigaDevice Semiconductor GD32F20 Series

Page 1 GigaDevice Semiconductor Inc. GD32F20x ™ ® Cortex -M3 32-bit MCU User Manual Revision 2.2 ( Oct. 2019 )
Page 2: Table Of Contents
GD32F20x User Manual Table of Contents Table of Contents ........................2 List of Figures ........................20 List of Tables ......................... 28 1. System and memory architecture ................32 1.1. ARM Cortex-M3 processor ....................32 1.2. System architecture ......................33 1.3. Memory map ........................
Page 3 GD32F20x User Manual 2.4.5. Control register 0(FMC_CTL0) ....................... 56 2.4.6. Address register 0 (FMC_ADDR0)....................57 2.4.7. Option byte status register (FMC_OBSTAT) ................. 57 Erase/Program Protection register (FMC_WP) ................58 2.4.8. Unlock key register 1(FMC_KEY1) ....................58 2.4.9. Status register 1 (FMC_STAT1) ...................... 59 2.4.10.
Page 4 GD32F20x User Manual 5.2. Clock control unit (CCTL) ..................... 81 5.2.1. Overview ............................81 5.2.2. Characteristics........................... 83 Function overview ..........................83 5.2.3. 5.3. Register definition ......................88 5.3.1. Control register (RCU_CTL) ......................88 5.3.2. Configuration register 0 (RCU_CFG0) ..................90 5.3.3.
Page 5 GD32F20x User Manual 7. General-purpose and alternate-function I/Os (GPIO and AFIO) ......134 7.1. Overview ......................... 134 7.2. Characteristics ......................... 134 7.3. Function overview ......................134 GPIO pin configuration ........................136 7.3.1. External interrupt/event lines ......................136 7.3.2. Alternate functions (AF) ......................... 136 7.3.3.
Page 6 GD32F20x User Manual 7.5.15. AFIO port configuration register 2 (AFIO_PCF2) ............... 169 7.5.16. AFIO port configuration register 3 (AFIO_PCF3) ............... 171 7.5.17. AFIO port configuration register 4 (AFIO_PCF4) ............... 175 AFIO port configuration register 5 (AFIO_PCF5) ............... 178 7.5.18. 8. CRC calculation unit (CRC) ..................183 8.1.
Page 7 GD32F20x User Manual 10.9.2. CAU Status register 0 (CAU_STAT0) ..................208 10.9.3. CAU data input register (CAU_DI) ....................209 10.9.4. CAU data output register (CAU_DO) ................... 210 CAU DMA enable register (CAU_DMAEN) ................. 210 10.9.5. CAU interrupt enable register (CAU_INTEN) ................211 10.9.6.
Page 8 GD32F20x User Manual Register definition ....................240 12.5. 12.5.1. Interrupt flag register (DMA_INTF) ....................240 12.5.2. Interrupt flag clear register (DMA_INTC) ..................240 Channel x control register (DMA_CHxCTL)................241 12.5.3. Channel x counter register (DMA_CHxCNT) ................243 12.5.4. Channel x peripheral base address register (DMA_CHxPADDR) ........... 244 12.5.5.
Page 9 GD32F20x User Manual 14.5. ADC sync mode ......................268 14.5.1. Free mode ............................270 14.5.2. Regular parallel mode ........................270 Inserted parallel mode ........................271 14.5.3. Follow-up fast mode ........................271 14.5.4. Follow-up slow mode ........................272 14.5.5. Trigger rotation mode ........................273 14.5.6.
Page 10 GD32F20x User Manual 15.4.2. Software trigger register (DAC_SWT) ..................298 15.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH) ..........299 15.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ..........299 DAC0 8-bit right-aligned data holding register (DAC0_R8DH) ..........300 15.4.5. DAC1 12-bit right-aligned data holding register (DAC1_R12DH) ..........
Page 11 GD32F20x User Manual 17.4.10. RTC alarm low register (RTC_ALRML) ................... 324 TIMER ........................326 18.1. Advanced timer (TIMERx, x=0, 7) ................... 327 18.1.1. Overview ............................327 18.1.2. Characteristics..........................327 18.1.3. Block diagram ..........................328 Function overview ........................... 330 18.1.4. Register definition ........................... 359 18.1.5.
Page 12 GD32F20x User Manual 19.3.6. Hardware flow control ........................495 19.3.7. Multi-processor communication ....................496 19.3.8. LIN mode ............................497 Synchronous mode ......................... 498 19.3.9. IrDA SIR ENDEC mode ......................499 19.3.10. Half-duplex communication mode .................... 500 19.3.11. Smartcard (ISO7816-3) mode ....................500 19.3.12.
Page 13 GD32F20x User Manual 20.4.8. Clock configure register (I2C_CKCFG) ..................542 20.4.9. Rise time register (I2C_RT)......................543 Serial peripheral interface/Inter-IC sound (SPI/I2S) ......... 544 21.1. Overview ........................544 21.2. Characteristics ......................544 SPI characteristics .......................... 544 21.2.1. I2S characteristics .......................... 544 21.2.2.
Page 14 GD32F20x User Manual 21.11.10. Quad-SPI mode control register (SPI_QCTL) of SPI0 ............581 Digital camera interface(DCI) ................582 22.1. Overview ........................582 22.2. Characteristics ......................582 22.3. Block diagram ....................... 582 22.4. Signal description ......................583 22.5. Function overview ......................583 22.5.1.
Page 15 GD32F20x User Manual 23.6.1. Synchronous pulse size register (TLI_SPSZ) ................601 23.6.2. Back-porch size register (TLI_BPSZ) ..................601 23.6.3. Active size register (TLI_ASZ) ...................... 602 Total size register (TLI_TSZ) ......................602 23.6.4. Control register (TLI_CTL) ......................603 23.6.5. Reload layer register (TLI_RL) ..................... 604 23.6.6.
Page 16 GD32F20x User Manual 24.6.4. Single block or multiple block read ....................654 24.6.5. Stream write and stream read (MMC only) ................. 655 24.6.6. Erase ..............................657 Bus width selection ......................... 658 24.6.7. Protection management ......................... 658 24.6.8. Card Lock/Unlock operation ......................659 24.6.9.
Page 17 GD32F20x User Manual 26.1. Overview ........................747 26.2. Characteristics ......................747 26.3. Function overview ......................748 26.3.1. Working mode ..........................748 26.3.2. Communication modes ........................749 26.3.3. Data transmission ........................... 750 Data reception ..........................752 26.3.4. Filtering function ..........................753 26.3.5.
Page 18 GD32F20x User Manual 27.3.1. Interface configuration ........................785 27.3.2. MAC function overview ........................789 27.3.3. MAC statistics counters: MSC ...................... 800 Wake up management: WUM ....................... 801 27.3.4. Precision time protocol: PTP ......................804 27.3.5. DMA controller description ......................808 27.3.6.
Page 19 GD32F20x User Manual 27.4.34. PTP subsecond increment register (ENET_PTP_SSINC) ........... 856 27.4.35. PTP time stamp high register (ENET_PTP_TSH) ..............857 27.4.36. PTP time stamp low register (ENET_PTP_TSL) ..............857 PTP time stamp update high register (ENET_PTP_TSUH) ..........858 27.4.37. PTP time stamp update low register (ENET_PTP_TSUL) ........... 858 27.4.38.
Page 20: List Of Figures
GD32F20x User Manual List of Figures Figure 1-1. Cortex™-M3 block diagram ......................33 Figure 1-2. GD32F20x Connectivity line series system architecture ............34 Figure 2-1. Process of page erase operation ....................47 Figure 2-2. Process of mass erase operation ..................... 48 Figure 2-3.
Page 21 GD32F20x User Manual Figure 14-2. Single conversion mode ......................257 Figure 14-3. Continuous conversion mode ....................258 Figure 14-4. Scan conversion mode, continuous disable ..............259 Figure 14-5. Scan conversion mode, continuous enable ............... 260 Figure 14-6. Discontinuous conversion mode ..................260 Figure 14-7.
Page 22 GD32F20x User Manual Figure 18-14. EAPWM timechart ........................342 Figure 18-15. CAPWM timechart ........................342 Figure 18-16. Complementary output with dead-time insertion ............345 Figure 18-17. Output behavior in response to a break (The break high active) ........346 Figure 18-18. Example of counter operation in encoder interface mode ..........347 Figure 18-19.
Page 23 GD32F20x User Manual Figure 18-58. Input capture logic ......................... 434 Figure 18-59. Output-compare under three modes .................. 436 Figure 18-60. EAPWM timechart ........................437 Figure 18-61. CAPWM timechart ........................437 Figure 18-62. Restart mode .......................... 439 Figure 18-63. Pause mode ..........................439 Figure 18-64.
Page 24 GD32F20x User Manual Figure 20-6. I2C communication flow with 7-bit address ................ 521 Figure 20-7. I2C communication flow with 10-bit address (Master Transmit) ........521 Figure 20-8. I2C communication flow with 10-bit address (Master Receive) ........521 Figure 20-9. Programming model for slave transmitting ................ 524 Figure 20-10.
Page 25 GD32F20x User Manual Figure 21-34. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ..........................563 Figure 21-35. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ..........................563 Figure 21-36. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ..........................
Page 26 GD32F20x User Manual Figure 24-12. Read wait control by stopping SDIO_CLK ................ 662 Figure 24-13. Read wait operation using SDIO_DAT[2] ................662 Figure 24-14. Function2 read cycle inserted during function1 multiple read cycle ......663 Figure 24-15. Read Interrupt cycle timing ....................663 Figure 24-16.
Page 27 GD32F20x User Manual Figure 25-37. Process for self-refresh entry and exit ................723 Figure 25-38. Process for power-down entry and exit ................724 Figure 26-1. CAN module block diagram ....................748 Figure 26-2. Transmission register ......................750 Figure 26-3. State of transmission mailbox ....................751 Figure 26-4.
Page 28: List Of Tables
GD32F20x User Manual List of Tables Table 1-1 Memory map of GD32F20x devices ..................... 35 Table 1-2. Each block of SRAM........................39 Table 1-3. Boot modes ............................ 40 Table 1-4. Bootloader supported peripherals ..................... 40 Table 2-1. GD32F20x_CL ..........................45 Table 2-2.
Page 29 GD32F20x User Manual ..................146 Table 7-29. SPI0 alternate function remapping Table 7-30. SPI1/I2S1 alternate function remapping ................146 ................146 Table 7-31. SPI2/I2S2 alternate function remapping Table 7-32. CAN0 alternate function remapping ..................147 Table 7-33. CAN1 alternate function remapping ..................147 Table 7-34.
Page 30 GD32F20x User Manual Table 21-3. SPI operation modes ......................... 548 Table 21-4. SPI interrupt requests ....................... 556 Table 21-5. I2S bitrate calculation formulas ....................566 Table 21-6. Audio sampling frequency calculation formulas ..............566 Table 21-7. Direction of I2S interface signals for each operation mode ..........567 Table 21-8.
Page 31 GD32F20x User Manual Table 24-31. Lock card data structure ......................659 Table 24-32. SDIO_RESPx register at different response type .............. 670 Table 25-1. SDRAM mapping........................686 Table 25-2. NOR flash interface signals description................686 Table 25-3. PSRAM non-muxed signal description .................. 687 Table 25-4.
Page 32: System And Memory Architecture
GD32F20x User Manual System and memory architecture The system architecture of the GD32F20x series of devices that includes the ARM® Cortex™- M3 processor, bus architecture and memory organization will be described in the following sections. The Cortex™-M3 processor is a next generation processor core which offers many new features.
Page 33: System Architecture
GD32F20x User Manual Figure 1-1. Cortex™-M3 block diagram Cotex-M3 Interrupts INTNMI INTISR[239:0] Sleep CM3Core NVIC Debug SLEEPING SLEEPDEEP Trigger Istruction Data Trace port (serial wire or multi-pin) TPIU Private Peripheral (external) Private Peripheral Bus (internal) Table I-code bus Matrix D-code bus AHB-AP System bus JTAG...
Page 34: Memory Map
GD32F20x User Manual Figure 1-2. GD32F20x Connectivity line series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M3 Memory Controller Processor : 144MHz Dbus Fmax:120MHz EXMC Slave SRAM0 1.2V Slave Master SRAM1 NVIC Slave SRAM2 Slave HAU TRNG 8MHz DMA0(7 chs) Master...
Page 35: Table 1-1 Memory Map Of Gd32F20X Devices
GD32F20x User Manual address space which is the maximum address range of the Cortex™-M3 since it has a 32-bit bus address width. Additionally, a pre-defined memory map is provided by the Cortex™-M3 processor to reduce the software complexity of repeated implementation of different device vendors.
Page 36 GD32F20x User Manual Pre-defined Address Peripherals Regions 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF Reserved 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF 0x4002 1C00 - 0x4002 1FFF Reserved 0x4002 1800 - 0x4002 1BFF...
Page 37 GD32F20x User Manual Pre-defined Address Peripherals Regions 0x4001 1000 - 0x4001 13FF GPIOC 0x4001 0C00 - 0x4001 0FFF GPIOB 0x4001 0800 - 0x4001 0BFF GPIOA 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF Reserved...
Page 38: Bit-Banding
GD32F20x User Manual Pre-defined Address Peripherals Regions 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF Reserved SRAM 0x2002 0000 -0x2005 FFFF SRAM2 0x2001 C000 -0x2001 FFFF SRAM1 0x2000 0000 - 0x2001 BFFF SRAM0 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes...
Page 39: On-Chip Sram Memory
GD32F20x User Manual  bit_band_base is the starting address of the alias region.  byte_offset is the number of the byte in the bit-band region that contains the targeted bit.  bit_number is the bit position (0-7) of the targeted bit. For example, to access bit 7 of address 0x2000 0200, the bit-band alias is: bit_word_addr = 0x2200 0000 + (0x200 * 32) + (7 * 4) = 0x2200 401C……..(1-2) Writing to address 0x2200 401C will cause bit 7 of address 0x2000 0200 change while a read...
Page 40: Device Electronic Signature
GD32F20x User Manual Table 1-3. Boot modes Boot mode selection pins Selected boot source Boot1 Boot0 Main Flash Memory System Memory On-chip SRAM After power-on sequence or a system reset, the ARM® Cortex™-M3 processor fetches the top-of-stack value from address 0x0000 0000 and the base address of boot code from 0x0000 0004 in sequence.
Page 41: Memory Size Information
GD32F20x User Manual 1.5.1. Memory size information Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit) SRAM_SIZE [15:0] FLASH_SIZE [15:0] Bits Fields Descriptions 15:0 SRAM_ SIZE[15:0] SRAM memory size The value indicates the SRAM memory size of the device in Kbytes.
Page 42: System Configuration Registers
GD32F20x User Manual UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Address offset: 0x08 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID 1.6. System configuration registers Base address: 0x4002 103C This register has to be accessed by word(32-bit) Reserved...
Page 43 GD32F20x User Manual Reserved Must be kept at reset value Note: Only bit[7] can be read-modify-write, other bits are not permitted.
Page 44: Flash Memory Controller (Fmc)
GD32F20x User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time while CPU executes instructions stored in the first 384K(in case that flash size equal to 256K or 512K, all memory is no waiting time) bytes of the flash . It also provides page erase, mass erase, and word/half-word program operations for flash memory.
Page 45: Read Operations
GD32F20x User Manual Table 2-1. GD32F20x_CL size Block Name Address Range (bytes) Page 0 0x0800 0000 - 0x0800 07FF Page 1 0x0800 0800 - 0x0800 0FFF Page 2 0x0800 1000 - 0x0800 17FF Main Flash Block Page 255 0x0807 F800 - 0x0807 FFFF Page 256 0x0808 0000 - 0x0808 0FFF Page 257...
Page 46: Page Erase
GD32F20x User Manual For the GD32F20x_CL with flash more than 512KB, the FMC_CTL0 register is used to configure the operations to bank0 and the option bytes block, while FMC_CTL1 register is used to configure the program and erase operations to bank1. The lock/unlock mechanism of FMC_CTL1 register is similar to FMC_CTL0 register.
Page 47: Mass Erase
GD32F20x User Manual Figure 2-1. Process of page erase operation Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by setting START bit Is the BUSY bit is 0 Finish For the GD32F20x_CL with flash more than 512KB, FMC_STAT0 reflects the operation status...
Page 48: Figure 2-2. Process Of Mass Erase Operation
GD32F20x User Manual register if erase bank1 only. Set MER bits in FMC_CTL0 register and FMC_CTL1 register if erase entire flash.  Send the mass erase command to the FMC by setting the START bit in FMC_CTLx registers.  Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STATx registers.
Page 49: Main Flash Programming
GD32F20x User Manual 2.3.6. Main flash programming The FMC provides a 32-bit word/16-bit half word programming function which is used to modify the main flash memory contents. The following steps show the register access sequence of the word programming operation. ...
Page 50: Option Bytes Erase
GD32F20x User Manual Figure 2-3. Process of word program operation Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0 Finish For the GD32F20x_CL with flash more than 512KB, the program procedure applied to bank1 is similar to the procedure applied to bank0.
Page 51: Option Bytes Modify
GD32F20x User Manual FMC_CTL0 register.  Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT0 register.  Read and verify the Flash memory by using a DBUS access if required. When the operation is executed successful, the ENDF in FMC_STAT0 register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL0 register is set.
Page 52: Table 2-2. Option Byte
GD32F20x User Manual Table 2-2. Option byte Address Name Description 0x1fff f800 option byte Security Protection value 0xA5 : no security protection any value except 0xA5 : under security protection 0x1fff f801 SPC_N SPC complement value 0x1fff f802 USER [7:4]: reserved [3]: BB 0: boot from bank1 or bank0 if bank1 is void, when configured boot from main memory...
Page 53: Page Erase/Program Protection
GD32F20x User Manual 2.3.10. Page erase/program protection The FMC provides page erase/program protection functions to prevent inadvertent operations on the Flash memory. The page erase or program will not be accepted by the FMC on protected pages. If the page erase or program command is sent to the FMC on a protected page, the WPERR bit in the FMC_STATx registers will then be set by the FMC.
Page 54: Unlock Key Register 0(Fmc_Key0)
GD32F20x User Manual Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value WSCNT[2:0] Wait state counter These bits is set and reset by software. The WSCNT valid when WSEN bit in FMC_WSEN is set. 000: 0 wait state added 001: 1 wait state added 010: 2 wait state added 011~111:reserved...
Page 55: Status Register 0 (Fmc_Stat0)
GD32F20x User Manual OBKEY[31:16] OBKEY[15:0] Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_ CTL0 option bytes operation unlock key These bits are only be written by software. Write OBKEY[31:0] with keys to unlock option bytes command in FMC_CTL0 register. 2.4.4. Status register 0 (FMC_STAT0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 56: Control Register 0(Fmc_Ctl0)
GD32F20x User Manual 2.4.5. Control register 0(FMC_CTL0) Address offset: 0x10 Reset value: 0x0000 0080 This register has to be accessed by word (32-bit) Reserved Reserved ENDIE Reserved ERRIE OBWEN Reserved START OBER OBPG Reserved Bits Fields Descriptions 31:13 Reserved Must be kept at reset value ENDIE End of operation interrupt enable bit This bit is set or cleared by software...
Page 57: Address Register 0 (Fmc_Addr0)
GD32F20x User Manual 0: no effect 1: option bytes program command Reserved Must be kept at reset value Main flash mass erase for bank0 command bit This bit is set or cleared by software 0: no effect 1: main flash mass erase command for bank0 Main flash page erase for bank0 command bit This bit is set or clear by software 0: no effect...
Page 58: Erase/Program Protection Register (Fmc_Wp)
GD32F20x User Manual Reserved DATA[15:6] DATA[5:0] USER[7:0] OBERR Bits Fields Descriptions 31:26 Reserved Must be kept at reset value 25:10 DATA[15:0] Store DATA of option bytes block after system reset. USER[7:0] Store USER of option bytes block after system reset. Option bytes security protection code 0: no protection 1: protection...
Page 59: Status Register 1 (Fmc_Stat1)
GD32F20x User Manual KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL1 unlock register These bits are only be written by software Write KEY[31:0] with keys to unlock FMC_CTL1 register 2.4.10. Status register 1 (FMC_STAT1) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved...
Page 60: Control Register 1(Fmc_Ctl1)
GD32F20x User Manual 2.4.11. Control register 1(FMC_CTL1) Address offset: 0x50 Reset value: 0x0000 0080 This register has to be accessed by word (32-bit) Reserved Reserved ENDIE Reserved ERRIE Reserved START Reserved Bits Fields Descriptions 31:13 Reserved Must be kept at reset value ENDIE End of operation interrupt enable bit This bit is set or cleared by software...
Page 61: Address Register 1 (Fmc_Addr1)
GD32F20x User Manual 1: main flash page erase command for bank1 Main flash program for bank1 command bit This bit is set or clear by software 0: no effect 1: main flash program command for bank1 Note: This register should be reset after the corresponding flash operation completed 2.4.12.
Page 62: Product Id Register (Fmc_Pid)
GD32F20x User Manual register. It is necessary to writing 0x45670123 and 0xCDEF89AB to the FMC_KEYx register. 0: no wait state added when fetch flash 1: wait state added when fetch flash 2.4.14. Product ID register (FMC_PID) Address offset: 0x100 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) PID[31:16] PID[15:0]...
Page 63: Power Management Unit (Pmu)
GD32F20x User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32F20x series. Power management unit (PMU) provides three types of power saving modes, including Sleep mode, Deep-sleep mode and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 64: Battery Backup Domain
GD32F20x User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP WKUPR BREG WKUPN NRST WKUPF SLEEPING Cortex-M3 FWDGT SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K 3.3V PLLs LVD: Low Voltage Detector LDO: Voltage Regulator BPOR: V...
Page 65: Vdd /V Dda
GD32F20x User Manual register with an expected wakeup time and enable the wakeup function so that it can achieve the RTC timer wakeup event. After entering the power saving mode for a certain amount of time, the RTC will wake up the device when the time match event occurs. The details of the RTC configuration and operation will be described in the Real-time Clock(RTC).
Page 66: Figure 3-3. Waveform Of The Lvd Threshold
GD32F20x User Manual Figure 3-2. Waveform of the POR/PDR 600mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD is enabled by setting the LVDEN bit.
Page 67: Power Domain
GD32F20x User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply is implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V...
Page 68: Table 3-1. Power Saving Mode Summary
GD32F20x User Manual WFI or WFE instruction is executed.  Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits from the lowest priority ISR. Deep-sleep mode The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex™-M3. In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC8M, HXTAL and PLLs are disabled.
Page 69 GD32F20x User Manual Mode Sleep Deep-sleep Standby and PLL and PLL LDO Status On or in low power mode SLEEPDEEP = 1 SLEEPDEEP = 1 Configuration SLEEPDEEP = 0 STBMOD = 0 STBMOD = 1, WURST=1 Entry WFI or WFE WFI or WFE WFI or WFE Any interrupt from EXTI...
Page 70: Register Definition
GD32F20x User Manual 3.4. Register definition PMU start address: 0x4000 7000 3.4.1. Control register (PMU_CTL) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved BKPWEN LVDT[2:0] LVDEN STBRST...
Page 71: Control And Status Register (Pmu_Cs)
GD32F20x User Manual 0: No effect 1: Reset the wakeup flag This bit is always read as 0. STBMOD Standby Mode 0: Enter the Deep-sleep mode when the Cortex™-M3 enters SLEEPDEEP mode 1: Enter the Standby mode when the Cortex™-M3 enters SLEEPDEEP mode LDOLP LDO Low Power Mode 0: The LDO operates normally during the Deep-sleep mode...
Page 72 GD32F20x User Manual 0: The device has not entered the Standby mode 1: The device has been in the Standby mode This bit is cleared only by a POR/PDR or by setting the STBRST bit in the PMU_CTL register Wakeup Flag 0: No wakeup event has been received 1: Wakeup event occurred from the WKUP pin or the RTC wakeup event including RTC Tamper event, RTC alarm event，RTC Time Stamp event or RTC Wakeup...
Page 73: Backup Registers (Bkp)
GD32F20x User Manual Backup registers (BKP) 4.1. Overview The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down. The Backup registers have forty two 16-bit (84 bytes) registers that can be used to store and protect user application data. Wake-up action from Standby mode or system reset do not affect these registers.
Page 74: Tamper0 Detection
GD32F20x User Manual 4.3.2. Tamper0 detection In order to protect the important user data, the MCU provides the tamper detection function, and it can be independently enabled on TAMPER0 pin (PC13) by setting corresponding TPEN0 bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN0 bit, the result is used as tamper detection signal.
Page 75: Register Definition
GD32F20x User Manual 4.4. Register definition BPK start address: 0x4000 6C00 4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) DATA [15:0] Bits Fields...
Page 76: Tamper Pin Control Register0 (Bkp_Tpctl0)
GD32F20x User Manual This bit is reset only by a Backup domain reset. ASOEN RTC alarm or second signal output enable 0: Disable RTC alarm or second output 1: Enable RTC alarm or second output When enable, the TAMPER0 pin is used as RTC output. This bit is reset only by a Backup domain reset.
Page 77 GD32F20x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) TIF1 TEF1 Reserved TIF0 TEF0 TPIE1 TIR1 TER1 Reserved TPIE0 TIR0 TER0 Bits Fields Descriptions TIF1 Tamper1/waveform detect interrupt flag 0: No tamper1 interrupt occurred 1: A tamper1 interrupt occurred This bit is reset by writing 1 to the TIR1 bit or the TPIE1 bit being 0.
Page 78: Tamper Pin Control Register1 (Bkp_Tpctl1)
GD32F20x User Manual 0: Disable the tamper0 interrupt 1: Enable the tamper0 interrupt This bit is reset only by a system reset and wake-up from Standby mode. TIR0 Tamper0 interrupt reset 0: No effect 1: Reset the TIF0 bit This bit is always read as 0. TER0 Tamper0 event reset 0: No effect...
Page 79 GD32F20x User Manual on the TAMPER1 pin resets all data of the BKP_DATAx register. Reserved Must be kept at reset value...
Page 80: Reset And Clock Unit (Rcu)
GD32F20x User Manual Reset and clock unit (RCU) 5.1. Reset control unit (RCTL) 5.1.1. Overview GD32F20x Reset Control includes three control modes: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the Backup domain.
Page 81: Clock Control Unit (Cctl)
GD32F20x User Manual A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset). Figure 5-1. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us System Reset FWDGT_RSTn pulse generator SW_RSTn OB_STDBY_RSTn...
Page 82: Figure 5-2. Clock Tree
GD32F20x User Manual Figure 5-2. Clock tree CK_HXTAL PLLTR prescaler TLI prescaler VCO input clock ×49,50, PLLT prescaler CK_TLI CK_PLLTR CK_VCO PLLT input clock (PLLTRPSC (TLIPSC ) …,432 (PLLTPSC ÷2,3...7 ÷2,4,8,16 ÷2,3...63 CK_IRC8M PLLTSEL PLLTMF (to FMC) CK_USBFS(=48 MHz) USBFS or CK_TRNG(<=48 MHz) Prescaler SCS[1:0]...
Page 83: Characteristics
GD32F20x User Manual The ADCs are clocked by the clock of APB2 divided by 2, 4, 6, 8, 12 or 16, which defined by ADCPSC in RCU_CFG0. The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB prescaler is not 1).
Page 84: Figure 5-3. Hxtal Clock Source
GD32F20x User Manual Figure 5-3. HXTAL clock source The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register RCU_CTL. The HXTALSTB flag in control register RCU_CTL indicates if the high- speed external crystal oscillator is stable. When the HXTAL is powered up, it will not be released for use until this HXTALSTB bit is set by the hardware.
Page 85 GD32F20x User Manual multiples of a fundamental reference frequency of 3 ~ 25 MHz. The PLL has three input clock sources: IRC8M/2 or HXTAL or PLL1. It can be choosed one of them as the input clock source of the PLL. The PLL can be switched on or off by using the PLLEN bit in the RCU_CTL register.
Page 86: Table 5-1. Clock Output 0 Source Select
GD32F20x User Manual The IRC40K can be trimmed by TIMER4_CH3, user can get the clocks frequency, and adjust the RTC and FWDGT counter. Please refer to TIMER4CH3_IREMAP in AFIO_PCF0 register. System clock (CK_SYS) selection After the system reset, the default CK_SYS source will be IRC8M and can be switched to HXTAL or CK_PLL by changing the system clock switch bits, SCS, in the Clock configuration register 0(RCU_CFG0).
Page 87: Table 5-2. Clock Output 1 Source Select
GD32F20x User Manual CK_OUT1 There are several clock signals can be selected via the CKOUT1 clock source selection bits, CKOUT1SEL, in the configuration register 2, RCU_CFG2. The corresponding GPIO pin should be configured in the properly Alternate Function I/O (AFIO) mode to output the selected clock signal.
Page 88: Register Definition
GD32F20x User Manual 5.3. Register definition RCU start address: 0x4002 1000 5.3.1. Control register (RCU_CTL) Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN PLLSTB PLLEN Reserved...
Page 89 GD32F20x User Manual 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock. Reset by hardware when entering Deep-sleep or Standby mode. 0: PLL is switched off 1: PLL is switched on 23:20...
Page 90: Configuration Register 0 (Rcu_Cfg0)
GD32F20x User Manual Reserved Must be kept at reset value. IRC8MSTB IRC8M Internal 8MHz RC Oscillator stabilization Flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator Enable Set and reset by software.
Page 91 GD32F20x User Manual 1010: EXT1 selected, to provide the external clock for ENET 1011: CK_PLL2 clock selected 23:22 USBFSPSC[1:0] USBFS and TRNG clock prescaler selection Set and reset by software. The USBFS clock must be 48MHz. These bits also control the random analog generator (TRNG) clock (≤48 MHz). These bits can’t be reset if the USBFS clock is enabled.
Page 92 GD32F20x User Manual 11101: (PLL source clock x 30) 11110: (PLL source clock x 31) 11111: (PLL source clock x 32) PREDV0_LSB The LSB of PREDV0 division factor This bit is the same bit as PREDV0 division factor bit [0] from RCU_CFG1. Changing the PREDV0 division factor bit [0] from RCU_CFG1, this bit is also changed.
Page 93: Interrupt Register (Rcu_Int)
GD32F20x User Manual 1000: (CK_SYS / 2) selected 1001: (CK_SYS / 4) selected 1010: (CK_SYS / 8) selected 1011: (CK_SYS / 16) selected 1100: (CK_SYS / 64) selected 1101: (CK_SYS / 128) selected 1110: (CK_SYS / 256) selected 1111: (CK_SYS / 512) selected SCSS[1:0] System clock switch status Set and reset by hardware to indicate the clock source of system clock.
Page 94 GD32F20x User Manual CKMIC HXTAL Clock Stuck Interrupt Clear Write 1 by software to reset the CKMIF flag. 0: Not reset CKMIF flag 1: Reset CKMIF flag PLL2STBIC PLL2 stabilization Interrupt Clear Write 1 by software to reset the PLL2STBIF flag. 0: Not reset PLL2STBIF flag 1: Reset PLL2STBIF flag PLL1STBIC...
Page 95 GD32F20x User Manual 0: Disable the PLL1 stabilization interrupt 1: Enable the PLL1 stabilization interrupt PLLSTBIE PLL Stabilization Interrupt Enable Set and reset by software to enable/disable the PLL stabilization interrupt. 0: Disable the PLL stabilization interrupt 1: Enable the PLL stabilization interrupt HXTALSTBIE HXTAL Stabilization Interrupt Enable Set and reset by software to enable/disable the HXTAL stabilization interrupt...
Page 96: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F20x User Manual 0: No PLL stabilization interrupt generated 1: PLL stabilization interrupt generated HXTALSTBIF HXTAL stabilization interrupt flag Set by hardware when the High speed 3 ~ 25 MHz crystal oscillator clock is stable and the HXTALSTBIE bit is set. Reset when setting the HXTALSTBIC bit by software.
Page 97 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value TIMER10RST Timer 10 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER10 TIMER9RST Timer 9 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER9 TIMER8RST...
Page 98 GD32F20x User Manual ADC0RST ADC0 reset This bit is set and reset by software. 0: No reset 1: Reset the ADC0 PGRST GPIO port G reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port G PFRST GPIO port F reset This bit is set and reset by software.
Page 99: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F20x User Manual 5.3.5. APB1 reset register (RCU_APB1RST) Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) CAN1 CAN0 UART4 UART3 USART2 USART1 Reserved DACRST PMURST BKPIRST Reserved I2C1RST I2C0RST Reserved WWDGT TIMER13 TIMER12 TIMER11 TIMER6...
Page 100 GD32F20x User Manual 0: No reset 1: Reset the I2C1 I2C0RST I2C0 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C0 UART4RST UART4 reset This bit is set and reset by software. 0: No reset 1: Reset the UART4 UART3RST UART3 reset...
Page 101: Ahb1 Enable Register (Rcu_Ahb1En)
GD32F20x User Manual This bit is set and reset by software. 0: No reset 1: Reset the TIMER13 TIMER12RST TIMER12 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER12 TIMER11RST TIMER11 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER11 TIMER6RST...
Page 102 GD32F20x User Manual This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) ENET Reserved RXEN ENET USBFS SRAM ENETEN Reserved Reserved SDIOEN Reserved EXMCEN Reserved CRCEN Reserved Reserved DMA1EN DMA0EN TXEN SPEN SPEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value ENETRXEN Ethernet RX clock enable This bit is set and reset by software.
Page 103: Apb2 Enable Register (Rcu_Apb2En)
GD32F20x User Manual 1: Enabled EXMC clock Reserved Must be kept at reset value CRCEN CRC clock enable This bit is set and reset by software. 0: Disabled CRC clock 1: Enabled CRC clock Reserved Must be kept at reset value FMCSPEN FMC clock enable when sleep mode This bit is set and reset by software to enable/disable FMC clock during Sleep...
Page 104 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value TIMER10EN TIMER10 clock enable This bit is set and reset by software. 0: Disabled TIMER10 clock 1: Enabled TIMER10 clock TIMER9EN TIMER9 clock enable This bit is set and reset by software. 0: Disabled TIMER9 clock 1: Enabled TIMER9 clock TIMER8EN...
Page 105 GD32F20x User Manual This bit is set and reset by software. 0: Disabled ADC1 clock 1: Enabled ADC1 clock ADC0EN ADC0 clock enable This bit is set and reset by software. 0: Disabled ADC0 clock 1: Enabled ADC0 clock PGEN GPIO port G clock enable This bit is set and reset by software.
Page 106: Apb1 Enable Register (Rcu_Apb1En)
GD32F20x User Manual 1: Enabled Alternate Function IO clock 5.3.8. APB1 enable register (RCU_APB1EN) Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) UART4 UART3 USART2 USART1 Reserved DACEN PMUEN BKPIEN CAN1EN CAN0EN Reserved I2C1EN I2C0EN...
Page 107 GD32F20x User Manual I2C1EN I2C1 clock enable This bit is set and reset by software. 0: Disabled I2C1 clock 1: Enabled I2C1 clock I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software.
Page 108 GD32F20x User Manual 10:9 Reserved Must be kept at reset value TIMER13EN TIMER13 clock enable This bit is set and reset by software. 0: Disabled TIMER13 clock 1: Enabled TIMER13 clock TIMER12EN TIMER12 clock enable This bit is set and reset by software. 0: Disabled TIMER12 clock 1: Enabled TIMER12 clock TIMER11EN...
Page 109: Backup Domain Control Register (Rcu_Bdctl)
GD32F20x User Manual 5.3.9. Backup domain control register (RCU_BDCTL) Address offset: 0x20 Reset value: 0x0000 0018, reset by Backup domain Reset. This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Note: The LXTALEN, LXTALBPS, LXTALDRI, RTCSRC and RTCEN bits of the Backup domain control register (RCU_BDCTL) are only reset after a Backup domain Reset.
Page 110: Reset Source/Clock Register (Rcu_Rstsck)
GD32F20x User Manual 00: lower driving capability 01: medium low driving capability 10: medium high driving capability 11: higher driving capability (reset value) Note: The LXTALDRI is not in bypass mode. LXTALBPS LXTAL bypass mode enable Set and reset by software. 0: Disable the LXTAL Bypass mode 1: Enable the LXTAL Bypass mode LXTALSTB...
Page 111 GD32F20x User Manual Set by hardware when a window watchdog timer reset generated. Reset by writing 1 to the RSTFC bit. 0: No window watchdog reset generated 1: Window watchdog reset generated FWDGTRSTF Free watchdog timer reset flag Set by hardware when free watchdog timer reset generated.
Page 112: Ahb1 Reset Register (Rcu_Ahb1Rst)
GD32F20x User Manual 5.3.11. AHB1 reset register (RCU_AHB1RST) Address offset: 0x28 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Reserved ENET USBFS Reserved Reserved Reserved Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ENETRST ENET reset This bit is set and reset by software.
Page 113 GD32F20x User Manual 31:19 Reserved Must be kept at reset value I2S2SEL I2S2 clock source selection Set and reset by software to control the I2S2 clock source. 0: System clock selected as I2S2 source clock 1: (CK_PLL2 x 2) selected as I2S2 source clock I2S1SEL I2S1 clock source selection Set and reset by software to control the I2S1 clock source.
Page 114: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F20x User Manual PREDV1[3:0] PREDV1 division factor This bit is set and reset by software. These bits can be written when PLL1 and PLL2 are disable. 0000: PREDV1 input source clock not divided 0001: PREDV1 input source clock divided by 2 0010: PREDV1 input source clock divided by 3 0011: PREDV1 input source clock divided by 4 0100: PREDV1 input source clock divided by 5...
Page 115: Ahb2 Enable Register (Rcu_Ahb2En)
GD32F20x User Manual Reset value: 0x0000 0000. This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Reserved Reserved DSLPVS[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value DSLPVS[2:0] Deep-sleep mode voltage register These bits is set and reset by software 000 : The core voltage is 1.2V in Deep-sleep mode 001 : The core voltage is 1.1V in Deep-sleep mode 010 : The core voltage is 1.0V in Deep-sleep mode...
Page 116: Apb2 Additional Enable Register (Rcu_Addapb2En)
GD32F20x User Manual 1: Enabled HAU clock CAUEN CAU clock enable This bit is set and reset by software. 0: Disabled CAU clock 1: Enabled CAU clock Reserved Must be kept at reset value DCIEN DCI clock enable This bit is set and reset by software. 0: Disabled DCI clock 1: Enabled DCI clock 5.3.15.
Page 117: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32F20x User Manual USART5EN USART5 clock enable This bit is set and reset by software. 0: Disabled USART5 clock 1: Enabled USART5 clock 23:0 Reserved Must be kept at reset value 5.3.16. APB1 additional enable register (RCU_ADDAPB1EN) Address offset: 0x68 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) UART7...
Page 118: Apb2 Additional Reset Register (Rcu_Addapb2Rst)
GD32F20x User Manual This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Reserved Reserved TRNGRST HAURST CAURST Reserved DCIRST Bits Fields Descriptions 31:7 Reserved Must be kept at reset value TRNGRST TRNG reset This bit is set and reset by software. 0: No reset 1: Reset the TRNG HAU RST...
Page 119: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32F20x User Manual Bits Fields Descriptions PIRST GPIO port I reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port I PHRST GPIO port H reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port H 29:27...
Page 120: Configuration Register 2 (Rcu_ Cfg2)
GD32F20x User Manual 1: Reset the UART7 UART6RST UART6 reset This bit is set and reset by software. 0: No reset 1: Reset the UART6 29:24 Reserved Must be kept at reset value I2C2RST I2C2 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C2 22:0...
Page 121: Pllt Control Register (Rcu_Plltctl)
GD32F20x User Manual Set and reset by software. 000000: The CK_OUT1 is divided by 1 000001: The CK_OUT1 is divided by 2 000010: The CK_OUT1 is divided by 3 111111: The CK_OUT1 is divided by 64 Reserved Must be kept at reset value CKOUT0DIV[5:0] The CK_OUT0 divider which the CK_OUT0 frequency can be reduced Set and reset by software.
Page 122: Pllt Interrupt Register (Rcu_Plltint)
GD32F20x User Manual 5.3.22. PLLT interrupt register (RCU_PLLTINT) Address offset: 0x94 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) PLLTSTB Reserved Reserved PLLTSTB PLLTSTB Reserved Reserved Reserved Bits Fields Descriptions 31:23 Reserved Must be kept at reset value PLLTSTBIC PLLT stabilization Interrupt clear Write 1 by software to reset the PLLTSTBIF flag.
Page 123 GD32F20x User Manual PLLTSEL PLLTRPSC[2:0] Reserved TLIPSC[1:0] Reserved PLLTMF[8:0] PLLTPSC[5:0] Bits Fields Descriptions PLLTSEL PLLT clock source select This bit can be written only when PLLT is disabled 0: select CK_IRC8M 1: select CK_HXTAL 30:28 PLLTRPSC[2:0] PLLTR prescaler selection Set and reset by software to control the TLI clock frequency. These bits should be written when the PLLT is disabled.
Page 124 GD32F20x User Manual 011000000: PLLTMF = 192 011000001: PLLTMF = 193 110110000: PLLTMF = 432 110110000: PLLTMF = 433, wrong configuration 111111111: PLLTMF = 511, wrong configuration PLLTPSC[5:0] PLLT prescaler selection These bits can be written only when PLLT is disabeled Note: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz.
Page 125: Interrupt/Event Controller(Exti)
GD32F20x User Manual Interrupt/event controller(EXTI) 6.1. Overview Cortex-M3 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. You can read the Technical Reference Manual of Cortex-M3 for more details about NVIC.
Page 126: Table 6-1. Nvic Exception Types In Cortex-M3
GD32F20x User Manual Table 6-1. NVIC exception types in Cortex-M3 Vector Exception Type Priority (a) Vector Address Description Number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault Programmable 0x0000_0010 Memory management MemManage Prefetch fault, memory access BusFault Programmable 0x0000_0014...
Page 127 GD32F20x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 15 DMA0 Channel4 global interrupt 0x0000_007C IRQ 16 DMA0 Channel5 global interrupt 0x0000_0080 IRQ 17 DMA0 Channel6 global interrupt 0x0000_0084 IRQ 18 ADC0 and ADC1 global interrupt 0x0000_0088 IRQ 19 CAN0 TX interrupts...
Page 128 GD32F20x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 49 SDIO global interrupt 0x0000_0104 IRQ 50 TIMER4 global interrupt 0x0000_0108 IRQ 51 SPI2 global interrupt 0x0000_010C IRQ 52 UART3 global interrupt 0x0000_0110 IRQ 53 UART4 global interrupt 0x0000_0114 IRQ 54 TIMER5 global interrupt...
Page 129: External Interrupt And Event (Exti) Block Diagram
GD32F20x User Manual 6.4. External interrupt and event (EXTI) block diagram Figure 6-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~19 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 6.5. External Interrupt and Event function overview The EXTI contains up to 20 independent edge detectors and generates interrupts request or event to the processer.
Page 130: Table 6-3. Exti Source
GD32F20x User Manual Table 6-3. EXTI source EXTI Line Number Source Attribute PA0/PB0/PC0/PD0/PE0/PF0/PG0/PH0/PI0 External PA1/PB1/PC1/PD1/PE1/PF1/PG1/PH1/PI1 External PA2/PB2/PC2/PD2/PE2/PF2/PG2/PH2/PI2 External PA3/PB3/PC3/PD3/PE3/PF3/PG3/PH3/PI3 External PA4/PB4/PC4/PD4/PE4/PF4/PG4/PH4/PI4 External PA5/PB5/PC5/PD5/PE5/PF5/PG5/PH5/PI5 External PA6/PB6/PC6/PD6/PE6/PF6/PG6/PH6/PI6 External PA7/PB7/PC7/PD7/PE7/PF7/PG7/PH7/PI7 External PA8/PB8/PC8/PD8/PE8/PF8/PG8/PH8/PI8 External PA9/PB9/PC90/PD9/PE9/PF9/PG9/PH9/PI9 External PA10/PB10/PC10/PD10/PE10/PF10/PG10/PH10/PI10 External PA11/PB11/PC11/PD11/PE11/PF11/PG11/PH11/PI11 External PA12/PB12/PC12/PD12/PE12/PF12/PG12/PH12 External PA13/PB13/PC13/PD13/PE13/PF13/PG13/PH13 External PA14/PB14/PC14/PD14/PE14/PF14/PG14/PH14 External PA15/PB15/PC15/PD15/PE15/PF15/PG15/PH15...
Page 131: Register Definition
GD32F20x User Manual 6.6. Register definition EXTI start address: 0x4001 0400 6.6.1. Interrupt enable register (EXTI_INTEN) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7...
Page 132: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F20x User Manual 6.6.3. Rising edge trigger enable register (EXTI_RTEN) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6 RTEN5 RTEN4 RTEN3...
Page 133: Pending Register (Exti_Pd)
GD32F20x User Manual This register has to be accessed by word(32-bit) Reserved SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:20 Reserved Must be kept at reset value 19: 0 SWIEVx Interrupt/Event software trigger...
Page 134: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32F20x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 7.1. Overview There are up to 140 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~ PH15 and PI0 ~ PI11 for the device to implement logic input/output functions.
Page 135: Figure 7-1. The Basic Structure Of A Standard I/O And Five-Volt Tolerant I/O Port
GD32F20x User Manual mode by two GPIO configuration registers (GPIOx_CTL0/GPIOx_CTL1), and two 32-bits data registers (GPIOx_ISTAT and GPIOx_OCTL).Table 7-1. GPIO configuration table shows the details. Table 7-1. GPIO configuration table Configuration mode CTL[1:0] MD[1:0] OCTL don’t care Analog don’t care Input floating Input Input pull-down...
Page 136: Gpio Pin Configuration
GD32F20x User Manual 7.3.1. GPIO pin configuration During or just after the reset period, the alternative functions are all inactive, and the GPIO ports are configured in input floating mode, which disables Pull-Up (PU)/Pull-Down (PD) resistors. But the JTAG/Serial-Wired Debug pins are in input PU/PD mode after reset: PA15: JTDI in PU mode.
Page 137: Output Configuration
GD32F20x User Manual Figure 7-2. Input configuration shows the input configuration. Figure 7-2. Input configuration 1. V dedicated for five-volt tolerant I/Os and is different from V dd_FT 7.3.5. Output configuration When GPIO pin is configured as output:  The schmitt trigger input is enabled. ...
Page 138: Analog Configuration
GD32F20x User Manual 1. V dedicated for five-volt tolerant I/Os and is different from V dd_FT 7.3.6. Analog configuration When GPIO pin is used as analog configuration:  The weak pull-up and pull-down resistors are disabled.  The output buffer is disabled. ...
Page 139: Io Pin Function Selection
GD32F20x User Manual Figure 7-5. Alternate function configuration 1. V dedicated for five-volt tolerant I/Os and is different from V dd_FT 7.3.8. IO pin function selection Each IO pin can implement many functions, each function selected by GPIO registers. GPIO: Each IO pin can be used for GPIO input function by configuring MDy bits to 0b00 in GPIOx_CTL0/GPIOx_CTL1 registers.
Page 140: Remapping Function I/O And Debug Configuration
GD32F20x User Manual 7.4. Remapping function I/O and debug configuration 7.4.1. Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each I/O pin can be configured to have up to four different functions by setting the AFIO Port Configuration Register (AFIO_PCF0/AFIO_PCF1).
Page 141: Adc Af Remapping
GD32F20x User Manual Table 7-3. Debug port mapping SWJ I/O pin assigned SWJ _CFG PA13/ PA14/ PB3/ JTDO/ Available debug ports PA15/ PB4/ [2:0] JTMS/ JTCK/S TRACE JTDI NJTRST SWDIO WCLK Full SWJ (JTAG-DP + SW-DP) ● ● ● ● ●...
Page 142: Timer Af Remapping
GD32F20x User Manual 7.4.5. TIMER AF remapping Table 7-8. TIMER0 alternate function remapping TIMER0_REMAP [1:0] TIMER0_REMAP [1:0] = TIMER0_REMAP [1:0] = Alternate function = “00” (no remap) “01” (partial remap) “11” (full remap) TIMER0_ETI PA12 TIMER0_CH0 TIMER0_CH1 PE11 TIMER0_CH2 PA10 PE13 TIMER0_CH3 PA11...
Page 143: Table 7-12. Timer4 Alternate Function Remapping
GD32F20x User Manual Table 7-12. TIMER4 alternate function remapping Alternate TIMER4CH3_ TIMER4CH3_ TIMER4_ TIMER4_ function IREMAP = 0 IREMAP = 1 REMAP = 0 REMAP = 1 TIMER4_CH0 PH10 TIMER4_CH1 PH11 TIMER4_CH2 PH12 IRC40K internal clock TIMER4_CH3 is is connected to TIMER4_CH3 connected to PA3 TIMER4_CH3 input...
Page 144: Usart Af Remapping
GD32F20x User Manual Table 7-17. TIMER11 alternate function remapping Alternate function TIMER11_REMAP = 0 TIMER11_REMAP = 1 TIMER11_CH0 PB14 TIMER11_CH1 PB15 1. Refer to the AF remap and debug I/O configuration register 1(AFIO_ PCF5) Table 7-18. TIMER12 alternate function remapping Alternate function TIMER12_REMAP = 0 TIMER12_REMAP = 1...
Page 145: I2C Af Remapping
GD32F20x User Manual Remap available only for 100-pin, 144-pin and 176-pin packages Table 7-23. UART3 alternate function remapping Alternate function UART3_REMAP = 0 UART3_REMAP = 1 UART3_TX PC10 UART3_RX PC11 Table 7-24. USART5 alternate function remapping Alternate function USART5_XX_REMAP = 0 USART5_XX_REMAP = 1 USART5_TX PG14...
Page 146: Spi Af Remapping
GD32F20x User Manual Alternate function I2C2_REMAP1 = 1 I2C2_REMAP2 = 1 I2C2_SMBA 7.4.8. SPI AF remapping Table 7-29. SPI0 alternate function remapping Alternate function SPI0_REMAP = 0 SPI0_REMAP = 1 SPI0_NSS PA15 SPI0_SCK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 Refer to AFIO port configuration register 0 (AFIO_ PCF0). Table 7-30.
Page 147: Ethernet Af Remapping
GD32F20x User Manual Table 7-32. CAN0 alternate function remapping CAN0_REMAP CAN0_REMAP CAN0_REMAP CAN0_ADD Alternate function [1:0] = “00” [1:0] = “10” [1:0] = “11” _REMAP = “1” CAN0_RX PA11 CAN0_TX PA12 PH13 1. This remapping is available only on 100-pin packages, when PD0 and PD1 are not remapped on OSC_IN and OSC_OUT.
Page 148: Dci Af Remapping
GD32F20x User Manual 7.4.11. DCI AF remapping Table 7-35. DCI alternate function remapping DCI_Dx_ DCI_Dx_ DCI_Dx_ DCI_Dx_ Alternate function REMAP = “00” REMAP = “01” REMAP = “10” REMAP = “11” DCI_D0 DCI_D1 PA10 PH10 DCI_Dx_ DCI_Dx_ DCI_Dx_ DCI_Dx_ Alternate function REMAP = “00”...
Page 149: Clk Pins Af Remapping
GD32F20x User Manual TLI_G3 PG10 / PE11 PH14 TLI_G4 PB10 PH15 TLI_G5 PB11 TLI_G6 TLI_G7 TLI_B0 AFIO_PCF3 AFIO_PCF4 Alternate function TLI_xx_Pn_ REMAP = 1 TLI_xx_Pn_ REMAP = 1 TLI_B1 PG12 TLI_B2 PD6 / PG10 TLI_B3 PD10 / PG11 TLI_B4 PE12 PI4 / PG12 TLI_B5 TLI_B6...
Page 150: Table 7-38. Osc Pins Configuration 1
GD32F20x User Manual Table 7-38. OSC pins configuration 1 Alternate function PD01_REMAP = 0 PD01_REMAP = 1 OSC_IN OSC_OUT Table 7-39. OSC pins configuration 2 Alternate function PH01_REMAP = 0 PH01_REMAP = 1 OSC_IN OSC_OUT 1. Only for 176 pin packages, PH0/PH1 default to OSC_IN, OSC_OUT, when PH01_REMAP =1, PH0/PH1 is general-purpose IO port.
Page 151: Register Definition
GD32F20x User Manual 7.5. Register definition GPIO start address: 0x4001 0800 7.5.1. Port control register 0 (GPIOx_CTL0, x=A..I) Address offset: 0x00 Reset value: 0x4444 4444 This register has to be accessed by word (32-bit). CTL7[1:0] MD7[1:0] CTL6[1:0] MD6[1:0] CTL5[1:0] MD5[1:0] CTL4[1:0] MD4[1:0] CTL3[1:0]...
Page 152 GD32F20x User Manual These bits are set and cleared by software refer to MD0[1:0]description 15:14 CTL3[1:0] Port 3 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 13:12 MD3[1:0] Port 3 mode bits These bits are set and cleared by software refer to MD0[1:0]description 11:10 CTL2[1:0]...
Page 153: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32F20x User Manual 7.5.2. Port control register 1 (GPIOx_CTL1, x=A..I) Address offset: 0x04 Reset value: 0x4444 4444 This register has to be accessed by word (32-bit). CTL15[1:0] MD15[1:0] CTL14[1:0] MD14[1:0] CTL13[1:0] MD13[1:0] CTL12[1:0] MD12[1:0] CTL11[1:0] MD11[1:0] CTL10[1:0] MD10[1:0] CTL9[1:0] MD9[1:0] CTL8[1:0] MD8[1:0] Bits...
Page 154: Port Input Status Register (Gpiox_Istat, X=A
GD32F20x User Manual refer to CTL0[1:0]description 13:12 MD11[1:0] Port 11 mode bits These bits are set and cleared by software refer to MD0[1:0]description 11:10 CTL10[1:0] Port 10 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description MD10[1:0] Port 10 mode bits These bits are set and cleared by software...
Page 155: Port Output Control Register (Gpiox_Octl, X=A
GD32F20x User Manual 15:0 ISTATy Port input status(y=0..15) These bits are set and cleared by hardware 0: Input signal low 1: Input signal high 7.5.4. Port output control register (GPIOx_OCTL, x=A..I) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved OCTL15 OCTL14...
Page 156: Port Bit Clear Register (Gpiox_Bc, X=A
GD32F20x User Manual 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0 BOPy Port Set bit y(y=0..15) These bits are set and cleared by software 0: No action on the corresponding OCTLy bit 1: Set the corresponding OCTLy bit to 1 Note: if CRy and BOPy are set at the same time, BOPy has priority.
Page 157: Event Control Register (Afio_Ec)
GD32F20x User Manual 31:17 Reserved Must be kept at reset value Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can always be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked. 1: GPIO_LOCK register is locked until an MCU reset..
Page 158: Afio Port Configuration Register 0 (Afio_Pcf0)
GD32F20x User Manual Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal. 0000: Select Pin 0 0001: Select Pin 1 0010: Select Pin 2 … 1111: Select Pin 15 7.5.9. AFIO port configuration register 0 (AFIO_PCF0) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 159 GD32F20x User Manual SPI2_MISO/PB4, SPI2_MOSI-I2S_SD/PB5) 1: Full remap (SPI2_NSS-I2S2_WS/PA4, SPI2_SCK-I2S2_CK/PC10, SPI2_MISO/PC11, SPI2_MOSI-I2S_SD/PC12) Reserved Must be kept at reset value 26:24 SWJ_CFG[2:0] Serial wire JTAG configuration These bits are write-only (when read,the value is undefined).They are used to configure the SWJ and trace alternate function I/Os. The SWJ(Serial Wire JTAG) supports JTAG or SWD access to the Cortex debug port.
Page 160 GD32F20x User Manual external event inserted conversion is connected to TIM7_CH3. ADC0_ETRGREG_REMAP ADC 0 external trigger regular conversion remapping Set and cleared by software. The bit control the trigger input connected to ADC0 external trigger inserted conversion. When this bit is reset, the ADC0 external trigger inserted conversion to EXTI11.When this bit is set, the ADC0 external event inserted conversion is connected to TIM7_TRGO.
Page 161 GD32F20x User Manual 11: Full remap (TIMER2_CH0/PC6,TIMER2_CH1/PC7,TIMER2_CH2/PC8, TIMER2_CH3/PC9) TIMER1_REMAP [1:0] TIMER1 remapping These bits are set and cleared by software 00: No remap (TIMER1_CH0-TIMER1_ETI/PA0,TIMER1_CH1/PA1, TIMER1_CH2/PA2,TIMER1_CH3/PA3) 01: Partial remap 0 (TIMER1_CH0-TIMER1_ETI/PA15,TIMER1_CH1/PB3, TIMER1_CH2/PA2,TIMER1_CH3/PA3) 10: Partial remap 1 (TIMER1_CH0-TIMER1_ETI/PA0,TIMER1_CH1/PA1, TIMER1_CH2/PB10,TIMER1_CH3/PB11) 11: Full remap (TIMER1_CH0-TIMER1_ETI/PA15,TIMER1_CH1/PB3, TIMER1_CH2/PB10,TIMER1_CH3/PB11) TIMER0_REMAP [1:0] TIMER0 remapping...
Page 162: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32F20x User Manual This bit is set and cleared by software 0: No remap (USART0_TX/PA9, USART0_RX /PA10) 1: Remap (USART0_TX/PB6, USART0_RX /PB7) I2C0_REMAP I2C0 remapping This bit is set and cleared by software 0: No remap (I2C0_SCL/PB6, I2C0_SDA /PB7) 1: Remap (I2C0_SCL/PB8, I2C0_SDA /PB9) SPI0_REMAP SPI0 remapping This bit is set and cleared by software...
Page 163: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32F20x User Manual 0000: PA2 pin 0001: PB2 pin 0010: PC2 pin 0011: PD2 pin 0100: PE2 pin 0101: PF2 pin 0110: PG2 pin 0111: PH2 pin 1000: PI2 pin Other configurations are reserved. EXTI1_SS [3:0] EXTI 1 sources selection 0000: PA1 pin 0001: PB1 pin 0010: PC1 pin...
Page 164 GD32F20x User Manual EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 EXTI7_SS [3:0] EXTI 7 sources selection 0000: PA7 pin 0001: PB7 pin 0010: PC7 pin 0011: PD7 pin 0100: PE7 pin 0101: PF7 pin 0110: PG7 pin...
Page 165: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32F20x User Manual 0011: PD4 pin 0100: PE4 pin 0101: PF4 pin 0110: PG4 pin 0111: PH4 pin 1000: PI4 pin Other configurations are reserved. 7.5.12. EXTI sources selection register 2 (AFIO_EXTISS2) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI11_SS [3:0] EXTI10_SS [3:0]...
Page 166: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32F20x User Manual 1000: PI10 pin Other configurations are reserved. EXTI9_SS [3:0] EXTI 9 sources selection 0000: PA9 pin 0001: PB9 pin 0010: PC9 pin 0011: PD9 pin 0100: PE9 pin 0101: PF9 pin 0110: PG9 pin 0111: PH9 pin 1000: PI9 pin Other configurations are reserved.
Page 167: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32F20x User Manual 0001: PB15 pin 0010: PC15 pin 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: PG15 pin Other configurations are reserved. 11:8 EXTI14_SS [3:0] EXTI 14 sources selection 0000: PA14 pin 0001: PB14 pin 0010: PC14 pin 0011: PD14 pin 0100: PE14 pin 0101: PF14 pin...
Page 168 GD32F20x User Manual Reserved EXMC_NA TIMER13_R TIMER12_ TIMER10_ TIMER9_R TIMER8_R Reserved Reserved EMAP REMAP REMAP EMAP EMAP Bits Fields Descriptions 31:11 Reserved Must be kept at reset value EXMC_NADV EXMC_NADV connect/disconnect This bit is set and cleared by software, it controls the use of optional EXMC_NADV signal.
Page 169: Afio Port Configuration Register 2 (Afio_Pcf2)
GD32F20x User Manual Reserved Must be kept at reset value 7.5.15. AFIO port configuration register 2 (AFIO_PCF2) Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DCI_HSY PH01_ DCI_D13_ DCI_D12 DCI_D11_ DCI_D10_ DCI_D9_ DCI_D8_ DCI_D7_ Reserved...
Page 170 GD32F20x User Manual 01: DCI_D11 remapped to PF10 10: Reserved 11: DCI_D11 remapped to PH15 23:22 DCI_D10_ DCI_D10 remapping REMAP [1:0] This bit is set and cleared by software. 00: No remap (PB5) 01: DCI_D10 remapped to PD6 10: Reserved 11: DCI_D10 remapped to PI3 21:20 DCI_D9_...
Page 171: Afio Port Configuration Register 3 (Afio_Pcf3)
GD32F20x User Manual 00: No remap (PC11) 01: DCI_D4 remapped to PE4 10: Reserved 11: DCI_D4 remapped to PH14 DCI_D3_ DCI_D3 remapping REMAP [1:0] This bit is set and cleared by software. 00: No remap (PC9) 01: DCI_D3 remapped to PE1 10: DCI_D3 remapped to PG11 11: DCI_D3 remapped to PH12 DCI_D2_...
Page 172 GD32F20x User Manual TLI_B3_P TLI_B2_P TLI_G3_P TLI_CLK_ TLI_R7_P TLI_DE_ TLI_R7_P TLI_CLK_ TLI_DE_ TLI_B4_P TLI_G3_ TLI_G1_ TLI_G0_ TLI_B0_P TLI_B3_P TLI_B2_P PF10 PE14 PE13 PE11 _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP _REMAP TLI_G7_P TLI_R2_P TLI_G6_P TLI_HSY...
Page 173 GD32F20x User Manual _REMAP This bit is set and cleared by software. 0: TLI_ CLK not remapped to PE14 1: TLI_ CLK remapped to PE14 TLI_DE_PE13 TLI_DE_PE13 remapping _REMAP This bit is set and cleared by software. 0: TLI_ DE not remapped to PE13 1: TLI_ DE remapped to PE13 TLI_B4_PE12 TLI_B4_PE12 remapping...
Page 174 GD32F20x User Manual TLI_R2_PC10 TLI_R2_PC10 remapping _REMAP This bit is set and cleared by software. 0: TLI_ R2 not remapped to PC10 1: TLI_ R2 remapped to PC10 TLI_G6_PC7 TLI_G6_PC7 remapping _REMAP This bit is set and cleared by software. 0: TLI_ G6 not remapped to PC7 1: TLI_ G6 remapped to PC7 TLI_HSYNC_PC6...
Page 175: Afio Port Configuration Register 4 (Afio_Pcf4)
GD32F20x User Manual 1: TLI_ R5 remapped to PA12 TLI_R4_PA11 TLI_R4_PA11 remapping _REMAP This bit is set and cleared by software. 0: TLI_ R4 not remapped to PA11 1: TLI_ R4 remapped to PA11 TLI_R6_PA8 TLI_R6_PA8 remapping _REMAP This bit is set and cleared by software. 0: TLI_ R6 not remapped to PA8 1: TLI_ R6 remapped to PA8 TLI_G2_PA6...
Page 176 GD32F20x User Manual 31:25 Reserved Must be kept at reset value SPI2_MOSI_REMAP SPI2_MOSI remapping This bit is set and cleared by software. 0: SPI2_MOSI remapped to PD6 1: No effect, refer to SPI2_REMAP SPI1_SCK_REMAP SPI1_SCK remapping This bit is set and cleared by software. 0: No effect, refer to SPI1_NSCK _REMAP 1: SPI1_SCK remapped to PD3 TLI_R1_PI3...
Page 177 GD32F20x User Manual 0: TLI_ B4 not remapped to PI4 1: TLI_ B4 remapped to PI4 TLI_G7_PI2 TLI_G7_PI2 remapping _REMAP This bit is set and cleared by software. 0: TLI_ G7 not remapped to PI2 1: TLI_ G7 remapped to PI2 TLI_G6_PI1 TLI_G6_PI1 remapping _REMAP...
Page 178: Afio Port Configuration Register 5 (Afio_Pcf5)
GD32F20x User Manual _REMAP This bit is set and cleared by software. 0: TLI_ R3 not remapped to PH9 1: TLI_ R3 remapped to PH9 TLI_R2_PH8 TLI_R2_PH8 remapping _REMAP This bit is set and cleared by software. 0: TLI_ R2 not remapped to PH8 1: TLI_ R2 remapped to PH8 TLI_R1_PH3 TLI_R1_PH3 remapping...
Page 179 GD32F20x User Manual Bits Fields Descriptions EXMC_SDNE1_REM EXMC_SDNE1 remapping This bit is set and cleared by software 0: No remap (PH6) 1: EXMC_SDNE1 remapped to PB6 EXMC_SDNE0_REM EXMC_SDNE0 remapping This bit is set and cleared by software 0: No remap (PH3) 1: EXMC_SDNE0 remapped to PC2 EXMC_SDCKE1_RE EXMC_SDCKE1 remapping...
Page 180 GD32F20x User Manual 1: USART5_CK remapped to PG7 UART6_REMAP UART6 remapping This bit is set and cleared by software 0: No remap (UART6_RX/UART6_TX mapped on PE7/8) 1: UART6_RX/UART6_TX remapped to PF6/PF7 ENET ETH_RXD2/ ETH_RXD3/ ETH_ RX_ER remapping _RX_HI_REMAP This bit is set and cleared by software 0: No effect.
Page 181 GD32F20x User Manual 12:11 SPI1_IO_REMAP SPI1_MISO/SPI1_MOSI remapping [1:0] This bit is set and cleared by software 00/01: No remap. SPI1_MISO/SPI1_MOSI mapped on PB14/PB15 10: SPI1_MISO/SPI1_MOSI remapped to PI2/PI3. 11: SPI1_MISO/SPI1_MOSI remapped to PC2/PC3 10:9 SPI1_NSCK_REMAP SPI1_NSS/SPI1_SCK remapping [1:0] This bit is set and cleared by software 00/01: No remap.
Page 182 GD32F20x User Manual I2C2_REMAP1 I2C2 remapping 1 This bit is set and cleared by software 0: No remap 1: I2C2_SCL/I2C2_SDA/I2C2_SMBA remapped to PH7/PH8/PH9 I2C2_REMAP0 I2C2 remapping 0 This bit is set and cleared by software 0: No remap 1: I2C2_SCL/ I2C2_SDA / I2C2_ SMBA remapped to PA8/ PC9/ PA9...
Page 183: Crc Calculation Unit (Crc)
GD32F20x User Manual CRC calculation unit (CRC) 8.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 32 bit CRC code with fixed polynomial. 8.2.
Page 184: Function Overview
GD32F20x User Manual 8.3. Function overview  CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 185: Register Definition
GD32F20x User Manual 8.4. Register definition CRC start address: 0x4002 3000 8.4.1. Data register (CRC_DATA) Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA [31:16] DATA [15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads.
Page 186: Control Register (Crc_Ctl)
GD32F20x User Manual These bits are unrelated with CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register will take no effect to the byte. 8.4.3. Control register (CRC_CTL) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 187: True Random Number Generator (Trng)
GD32F20x User Manual True random number generator (TRNG) 9.1. Overview The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. 9.2. Characteristics  About 40 periods of TRNG_CLK are needed between two consecutive random numbers ...
Page 188: Operation Flow
GD32F20x User Manual TRNG_CLK (refer to Reset and clock unit (RCU) chapter), so that the quality of the generated random number depends on TRNG_CLK exclusively, no matter what HCLK frequency was set or not. The 32-bit value of LFSR will transfer into TRNG_DATA register after a sufficient number of seeds have been sent to the LFSR.
Page 189: Register Definition
GD32F20x User Manual 9.4. Register definition TRNG start address: 0x5006 0800 9.4.1. Control register (TRNG_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved TRNGEN Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value Interrupt enabled bit.
Page 190: Data Register (Trng_Data)
GD32F20x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value SEIF Seed error interrupt flag This bit will be set if more than 64 consecutive same bit or more than 32 consecutive 01(or 10) changing are detected. 0: No fault detected 1: Seed error has been detected.
Page 191 GD32F20x User Manual Bits Fields Descriptions 31:0 TRNDATA[31:0] 32-Bit Random data...
Page 192: Cryptographic Acceleration Unit (Cau)
GD32F20x User Manual Cryptographic Acceleration Unit (CAU) 10.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ...
Page 193: Cau Data Type And Initialization Vectors
GD32F20x User Manual  four 32-bit initialization vectors (IV) are used in CBC and CTR modes  8*32-bit input and output FIFO  Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping  Data can be transferred by DMA, CPU during interrupts, or without both of them 10.3.
Page 194: Initialization Vectors
GD32F20x User Manual Figure 10-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping 10.3.2. Initialization vectors The initialization vectors are used in CBC and CTR modes to XOR with data blocks. They are independent of plaintext and ciphertext, and the DATAM value will not affect them.
Page 195: Des/Tdes Cryptographic Acceleration Processor
GD32F20x User Manual Figure 10-3. CAU diagram CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_CTL CAU_STAT0 DMAEN INTEN INTF STAT1 KEY0..3 IV0..1 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Config 8*32 8*32 Data swapping Data swapping Cryptographic acceleration core (DES/TDES/AES) 10.4.1.
Page 196: Figure 10-4. Des/Tdes Ecb Encryption
GD32F20x User Manual DES/TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1. The output is fed back directly to next DEA and then decrypted using KEY2. After that, the output is fed back directly to the last DEA and encrypted with KEY3.
Page 197: Figure 10-5. Des/Tdes Ecb Decryption
GD32F20x User Manual Figure 10-5. DES/TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES/TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors.
Page 198: Figure 10-6. Des/Tdes Cbc Encryption
GD32F20x User Manual Figure 10-6. DES/TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES/TDES CBC decryption In DES/TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3.
Page 199: Aes Cryptographic Acceleration Processor
GD32F20x User Manual Figure 10-7. DES/TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext 10.4.2. AES cryptographic acceleration processor The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce.
Page 200: Figure 10-8. Aes Ecb Encryption
GD32F20x User Manual Figure 10-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption.
Page 201: Figure 10-10. Aes Cbc Encryption
GD32F20x User Manual AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the AEA and encrypted using the 128-, 192-, 256-bit key.
Page 202: Figure 10-11. Aes Cbc Decryption
GD32F20x User Manual plaintext is also obtained after data swapping according to the data type. The procedure of AES CBC mode decryption is illustrated in Figure 10-11. AES CBC decryption. Figure 10-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) SWAP...
Page 203: Operating Modes
GD32F20x User Manual Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext/ CAU_DO Plaintext 10.5. Operating modes Encryption Disable the CAU by resetting the CAUEN bit in the CAU_CTL register Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen.
Page 204: Cau Dma Interface
GD32F20x User Manual Decryption 1. Disable the CAU by resetting the CAUEN bit in the CAU_CTL register 2. Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen. 3. Configure the CAU_KEY0..3(H/L) registers according to the algorithm 4.
Page 205: Cau Interrupts
GD32F20x User Manual 10.7. CAU interrupts There are two types of interrupt registers in CAU, which are CAU_STAT1 and CAU_INTF. In CAU, the interrupt is used to indicate the situation of the input and output FIFO. Any of input and output FIFO interrupt can be enabled or disabled by configuring the Interrupt Enable register CAU_INTEN.
Page 206 GD32F20x User Manual prepare the key and initialization vectors. Then enable CAU by setting the CAUEN bit in the CAU_CTL register When data transfer is done by CPU access to CAU_DI and CAU_DO: 1. When the data transfer is done by CPU access, then wait for the fourth read of the CAU_DO register and before the next CAU_DI write access so that the message is suspended at the end of a block processing.
Page 207: Register Definition
GD32F20x User Manual 10.9. Register definition CAU start address: 0x5006 0000 10.9.1. CAU control register (CAU_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CAUEN FFLUSH Reserved KEYM[1:0] DATAM[1:0] ALGM[2:0] CAUDIR Reserved Bits Fields...
Page 208: Cau Status Register 0 (Cau_Stat0)
GD32F20x User Manual ALGM[2:0] Encryption/decryption algorithm mode, must be configured when BUSY=0 000: TDES-ECB with CAU_KEY1, 2, 3. Initialization vectors (CAU_IV0..1) are not used 001: TDES-CBC with CAU_KEY1, 2, 3. Initialization vectors (CAU_IV0) is used to XOR with data blocks 010: DES-ECB with only CAU_KEY1 Initialization vectors (CAU_IV0..1) are not used 011: DES-CBC with only CAU_KEY1...
Page 209: Cau Data Input Register (Cau_Di)
GD32F20x User Manual - CAU is disabled by CAUEN=0 or the processing has been completed. - No enough data or no enough space in the input/output FIFO to perform a data block 1: CAU is processing data or key derivation. Output FIFO is full 0: Output FIFO is not full 1: Output FIFO is full...
Page 210: Cau Data Output Register (Cau_Do)
GD32F20x User Manual 10.9.4. CAU data output register (CAU_DO) Address offset: 0x0C Reset value: 0x0000 0000 The data output register is a read only register. It is used to receive plaintext or ciphertext results from the output FIFO. Similar to CAU_DI, the MSB is read at first while the LSB is read at last.
Page 211: Cau Interrupt Enable Register (Cau_Inten)
GD32F20x User Manual 10.9.6. CAU interrupt enable register (CAU_INTEN) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved OINTEN IINTEN Bits Fields Descriptions 31:2 Reserved Must keep the reset value OINTEN OUT FIFO interrupt enable 0: OUT FIFO interrupt is disable 1: OUT FIFO interrupt is enable...
Page 212: Cau Interrupt Flag Register (Cau_Intf)
GD32F20x User Manual 0: IN FIFO interrupt not pending 1: IN FIFO interrupt flag pending 10.9.8. CAU interrupt flag register (CAU_INTF) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved OINTF IINTF Bits Fields...
Page 213 GD32F20x User Manual KEY1L[31:0] is used as AES_KEY[64:127], KEY2H[31:0] || KEY2L[31:0] is used as AES_KEY[128:191], and KEY3H[31:0] || KEY3L[31:0] is used as AES_KEY[192:255]. NOTE: “||” is a concatenation operator. For example, X || Y denotes the concatenation of two bit strings X and Y. CAU_KEY0H Address offset: 0x20 Reset value: 0x0000 0000...
Page 214 GD32F20x User Manual KEY1L[15:0] CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0] CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 KEY2L[31:16] KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 KEY3H[31:16] KEY3H[15:0] CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000 KEY3L[31:16]...
Page 215: Cau Initial Vector Registers (Cau_Iv0
GD32F20x User Manual KEY3L[15:0] Bits Fields Descriptions 31:0 KEY0...3(H/L) The key for DES, TDES, AES 10.9.10. CAU Initial vector registers (CAU_IV0..1(H/L)) Address offset: 0x40 to 0x4C Reset value: 0x0000 0000 This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0.
Page 216 GD32F20x User Manual Reset value: 0x0000 0000 IV1H[31:16] IV1H[15:0] CAU_IV1L Address offset: 0x4C Reset value: 0x0000 0000 IV1L[31:16] IV1L[15:0] Bits Fields Descriptions 31:0 IV0...1(H/L) The initialization vector for DES, TDES, AES...
Page 217: Hash Acceleration Unit (Hau)
GD32F20x User Manual Hash Acceleration Unit (HAU) 11.1. Overview The hash acceleration unit is used for information security. The secure hash algorithm (SHA- 1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash message authentication code (HMAC) algorithm are supported for various applications. The digest will be computed and the length is 160/224/256/128 bits for a message up to (264 - 1) bits computed by SHA-1, SHA-224, SHA-256 and MD5 algorithms respectively.
Page 218: Figure 11-1. Datam No Swapping And Half-Word Swapping
GD32F20x User Manual Figure 11-1. DATAM No swapping and Half-word swapping Figure 11-2. DATAM Byte swapping and Bit swapping illustrate the data swapping according to different data types. Figure 11-1. DATAM No swapping and Half-word swapping word0 word0 WORD 0 (MSB) word1 word1 WORD 1...
Page 219: Hau Core
GD32F20x User Manual 11.4. HAU core The hash acceleration unit is used to compute condensed information of input messages with secure hash algorithms. The digest result has a length of 160/224/256/128 bits for a message up to (264-1) bits computed by SHA-1, SHA-224, SHA256 and MD5 algorithms respectively. It can be used to generate or verify the signature of a message with a higher efficiency because of the much simpler of the information.
Page 220: Digest Computing
GD32F20x User Manual Data Padding Example: The input message is “HAU”, which ASCII hexadecimal code is: 484155 Then the VBL bits in the HAU_CFG register is set as decimal 24 because of the valid bit length. A “1” is added at bit location 24 then, and several “0” are padded so that the result modulo 512 is 448, the hexadecimal result is as follows: 48415580 00000000 00000000 00000000 00000000 00000000 00000000 00000000...
Page 221: Hash Mode
GD32F20x User Manual  The last block computing can be started when CALEN bit in the HAU_CFG register is 1. 11.4.3. Hash mode The hash mode is selected when the HMS bit in the HAU_CTL register is set as 0. And when the START bit in the HAU_CTL register is 1, SHA-1, SHA-224, SHA-256 and MD5 mode computation is chosen by the ALGM bits.
Page 222 GD32F20x User Manual HAU_INTEN. Value 1 of the register enable the interrupts. Input FIFO interrupt The input FIFO interrupt is asserted when there is enough space in the input FIFO, then DINT is asserted. Note if the input FIFO interrupt is disenabled by DIIE with a 0 value, the DINT is always de-asserted.
Page 223: Register Definition
GD32F20x User Manual 11.6. Register definition HAU start address: 0x5006 0400 11.6.1. HAU control register (HAU_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved ALGM[1] Reserved Reserved DINE NWIF[3:0] ALGM[0] DATAM[1:0] DMAE START Reserved...
Page 224: Hau Data Input Register (Hau_Di)
GD32F20x User Manual ALGM[0] Algorithm selection bit 0 This bit and bit 18 of CTL are written by software to select the SHA-1, SHA-224, SHA256 or the MD5 algorithm: 00: Select SHA-1 algorithm 01: Select MD5 algorithm 10: Select SHA224 algorithm 11: Select SHA256 algorithm HAU mode selection, must be changed when no computation is processing 0: HASH mode selected...
Page 225: Hau Configuration Register (Hau_Cfg)
GD32F20x User Manual This register has to be accessed by word (32-bit) DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Message data input When write to these registers, the current content pushed to IN FIFO and new value updates. When read, returns the current content. 11.6.3.
Page 226: Hau Data Output Register (Hau_Do0
GD32F20x User Manual 0x1F: Only bits [0] of the last data written to HAU_DI after data swapping are valid. Note: this bits must be configured before setting the CALEN bit. 11.6.4. HAU data output register (HAU_DO0..7) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) The data output registers are read only registers.
Page 227 GD32F20x User Manual DO2[15:0] HAU_DO3 Address offset: 0x18 and 0x31C DO3[31:16] DO3[15:0] HAU_DO4 Address offset: 0x1C and 0x320 DO4[31:16] DO4[15:0] HAU_DO5 Address offset: 0x324 DO5[31:16] DO5[15:0] HAU_DO6 Address offset: 0x328 DO6[31:16] DO6[15:0]...
Page 228: Hau Interrupt Enable Register (Hau_Inten)
GD32F20x User Manual HAU_DO7 Address offset: 0x32C DO7[31:16] DO7[15:0] Bits Fields Descriptions 31:0 DO0..7[31:0] message digest result of hash algorithm 11.6.5. HAU interrupt enable register (HAU_INTEN) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CCIE...
Page 229 GD32F20x User Manual Reserved Reserved BUSY DMAS CINT DINT rc_w0 rc_w0 Bits Fields Descriptions 31:4 Reserved Must keep the reset value BUSY Busy bit 0: No processing 1: Data block is in process DMAS DMA status 0: DMA is disabled (DMAE =0) and no transfer is processing 1: DMA is enabled (DMAE =1) or a transfer is processing CINT Digest calculation completion interrupt flag...
Page 230: Direct Memory Access Controller (Dma)
GD32F20x User Manual Direct memory access controller (DMA) 12.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 231: Block Diagram
GD32F20x User Manual 12.3. Block diagram Figure 12-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 232: Table 12-1. Dma Transfer Operations (Normal Mode)
GD32F20x User Manual transmission, the CNT bits indicate the remaining number of data items to be transferred. The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 233: Peripheral Handshake
GD32F20x User Manual Full_Data Mode In Full_Data mode, the transfer size of source and destination must not be equal and the transfer size of source must be 32-bit. If the transfer size of destination is 16-bit, each DMA transfer is achieved with one source operation followed by two destination operations. If the transfer size of destination is 8-bit, four destination operations are needed to complete one DMA transfer.
Page 234: Arbitration
GD32F20x User Manual Figure 12-2. Handshake mechanism Peripheral is ready to transmit Peripheral releases the or receive data, and assert the request signal when it receives Peripheral launches request signal to DMA the acknowledge signal the next request Peripheral Peripheral Peripheral request request request...
Page 235: Memory To Memory Mode
GD32F20x User Manual 12.4.6. Memory to memory mode The memory to memory mode is enabled by setting the M2M bit in the DMA_CHxCTL register. In this mode, the DMA channel can also work without being triggered by a request from a peripheral.
Page 236: Dma Request Mapping
GD32F20x User Manual Transfer error ERRIF ERRIFC ERRIE The DMA interrupt logic is shown in the Figure 12-3. DMA interrupt logic, an interrupt can be produced when any type of interrupt event occurs and enabled on the channel. Figure 12-3. DMA interrupt logic FTFIFx FTFIEx HTFIFx...
Page 237 GD32F20x User Manual request from peripheral for each channel of DMA1. Figure 12-4. DMA0 request mapping Hardware priority ADC0 TIMER1_CH2 high Channel 0 TIMER3_CH0 MEMTOMEM0 SPI0_RX USART2_TX TIMER0_CH0 Channel 1 TIMER1_UP TIMER2_CH2 MEMTOMEM2 MEMTOMEM1 SPI0_TX USART2_RX TIMER0_CH1 Channel 2 TIMER2_CH3 TIMER2_UP MEMTOMEM2 SPI1/I2S1_RX...
Page 238: Figure 12-5. Dma1 Request Mapping
GD32F20x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● ● ● ● ● ● ADC0 ADC0 ● ● ● SPI/I2S SPI0_RX SPI0_TX SPI1/I2S1_RX SPI1/I2S1_TX ● USART USART2_TX USART2_RX USART0_TX USART0_RX USART1_RX USART1_TX ●...
Page 239 GD32F20x User Manual Table 12-5. DMA1 requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER4_CH3 TIMER4_CH2 ● ● ● TIMER4 TIMER4_CH1 TIMER4_CH0 TIMER4_TG TIMER4_UP TIMER5/ TIMER5_UP/ ● ● ● ●...
Page 240: Register Definition
GD32F20x User Manual 12.5. Register definition DMA0 start address: 0x4002 0000 DMA1 start address: 0x4002 0400 12.5.1. Interrupt flag register (DMA_INTF) Address offset: 0x00 Reset value: 0x0000 0000 Reserved ERRIF6 HTFIF6 FTFIF6 GIF6 ERRIF5 HTFIF5 FTFIF5 GIF5 ERRIF4 HTFIF4 FTFIF4 GIF4 ERRIF3 HTFIF3...
Page 241: Channel X Control Register (Dma_Chxctl)
GD32F20x User Manual Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIFC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0 Bits Fields Descriptions 31:28 Reserved Keep at reset value 27/23/19/ ERRIFCx Clear bit for error flag of channel x (x=0…6)
Page 242 GD32F20x User Manual 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’. 11:10 MWIDTH[1:0] Transfer data size of memory...
Page 243: Channel X Counter Register (Dma_Chxcnt)
GD32F20x User Manual 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt Software set and cleared 0: Disable the channel error interrupt 1: Enable the channel error interrupt HTFIE Enable bit for channel half transfer finish interrupt Software set and cleared...
Page 244: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F20x User Manual by the previously programmed value if the channel is configured in circular mode. 12.5.5. Channel x peripheral base address register (DMA_CHxPADDR) x = 0...6, where x is a channel number Address offset: 0x10 + 0x14 × x Reset value: 0x0000 0000 PADDR[31:16] PADDR[15:0]...
Page 245: Dma Additional Configuration Register (Dma_Acfg)
GD32F20x User Manual bits are ignored. Access is automatically aligned to a word address. 12.5.7. DMA additional configuration register (DMA_ACFG) Address offset: 0x0300 Reset value: 0x0000 0000 This register is not sutiable for DMA0. Note: Reserved Reserved FD_CH5EN Reserved Bits Fields Descriptions 31:6...
Page 246: Debug (Dbg)
GD32F20x User Manual Debug (DBG) 13.1. Overview The GD32F20x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSightTM module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM Cortex-M3.
Page 247: Jtag Daisy Chained Structure
GD32F20x User Manual with two of five JTAG pin, which is SWDIO multiplexed with JTMS, SWCLK multiplexed with JTCK. The JTDO is also used as Trace async data output (TRACESWO) when async trace enabled. The pin assignment are: PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST...
Page 248: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32F20x User Manual debugger can debug in standby mode. When exit the standby mode, a system reset generated. When DSLP_HOLD bit in DBG control register (DBG_CTL) is set and entering the Deep- sleep mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in Deep-sleep mode.
Page 249: Register Definition
GD32F20x User Manual 13.4. Register definition 13.4.1. ID code register (DBG_ID) Address: 0xE004 2000 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software, These bits are unchanged constant 13.4.2.
Page 250 GD32F20x User Manual 0: no effect 1: hold the TIMER 9 counter for debug when core halted TIMER8_HOLD TIMER 8 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 8 counter for debug when core halted TIMER13_HOLD TIMER 13 hold bit This bit is set and reset by software...
Page 251 GD32F20x User Manual I2C1_HOLD I2C1 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C1 SMBUS timeout for debug when core halted I2C0_HOLD I2C0 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C0 SMBUS timeout for debug when core halted CAN0_HOLD...
Page 252 GD32F20x User Manual 10: Trace pin used in synchronous mode and the data length is 2 11: Trace pin used in synchronous mode and the data length is 4 TRACE_IOEN Trace pin allocation enable This bit is set and reset by software 0: Trace pin allocation disable 1: Trace pin allocation enable Reserved...
Page 253: Analog-To-Digital Converter (Adc)
GD32F20x User Manual Analog-to-digital converter (ADC) 14.1. Overview The 12-bit ADC is an analog-to-digital converter using the successive approximation method. It has 18 multiplexed channels making the ADC convert analog signals from 16 external channels, and 2 internal channels. The analog watchdog allows the application to detect whether the input voltage goes outside the user-defined higher or lower thresholds.
Page 254: Pins And Internal Signals
GD32F20x User Manual －analog watchdog event  Oversampler －16-bit data register －Oversampling ratio adjustable from 2 to 256x －Programmable data shift up to 8-bit  ADC supply requirements: 2.6V to 3.6V, and typical power supply voltage is 3.3V  ≤V ≤V ADC input range: V REFN...
Page 255: Function Overview
GD32F20x User Manual 14.4. Function overview Figure 14-1. ADC module block diagram Trig select Trig select Regular Inserted channels channels EOIC Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Injected data registers （16 bits x 4） Over ADC_IN15 SAR ADC...
Page 256: Adc Clock
GD32F20x User Manual Set RSTCLB (optional). Set CLB=1. Wait until CLB=0. 14.4.2. ADC clock The ADCCLK clock provided by the clock controller is synchronous with the AHB and APB2 clock. The maximum frequency is 28MHz. The RCU controller has a dedicated programmable prescaler for the ADC clock.
Page 257: Figure 14-2. Single Conversion Mode
GD32F20x User Manual Figure 14-2. Single conversion mode Sample Regular trigger Convert After conversion of a single regular channel, the conversion data will be stored in the ADC_RDATA register, the EOC will be set. An interrupt will be generated if the EOCIE bit is set.
Page 258: Figure 14-3. Continuous Conversion Mode
GD32F20x User Manual enabled when CTN bit in the ADC_CTL1 register is set. In this mode, the ADC performs conversion on the channel specified in the RSQ0[4:0]. When the ADCON has been set high, the ADC samples and converts specified channel, once the corresponding software trigger or external trigger is active.
Page 259: Figure 14-4. Scan Conversion Mode, Continuous Disable
GD32F20x User Manual trigger or external trigger is active. The conversion data will be stored in the ADC_RDATA or ADC_IDATAx register. After conversion of the regular or inserted channel group, the EOC or EOIC will be set. An interrupt will be generated if the EOCIE or EOICIE bit is set. The DMA bit in ADC_CTL1 register must be set when the regular channel group works in scan mode.
Page 260: Figure 14-5. Scan Conversion Mode, Continuous Enable
GD32F20x User Manual Clear the EOC/EOIC flag by writing 0 to them Figure 14-5. Scan conversion mode, continuous enable Discontinuous mode For regular channel group, the discontinuous conversion mode will be enabled when DISRC bit in the ADC_CTL0 register is set. In this mode, the ADC performs a short sequence of n conversions (n<=8) which is a part of the sequence of conversions selected in the ADC_RSQ0~ADC_RSQ2 registers.
Page 261: Inserted Channel Management
GD32F20x User Manual Configure DISNUM[2:0] bits in the ADC_CTL0 register Configure ADC_RSQx and ADC_SAMPTx registers Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need Prepare the DMA module to transfer data from the ADC_RDATA (refer to the spec of the module).
Page 262: Analog Watchdog
GD32F20x User Manual The auto insertion mode cannot be enabled when the discontinuous conversion mode is set. Triggered insertion If the ICA bit is cleared, the triggered insertion occurs if a software or external trigger occurs during the regular group channel conversion. In this situation, the ADC aborts from the current conversion and starts the conversion of inserted channel sequence.
Page 263: Figure 14-9. Data Alignment Of 12-Bit Resolution
GD32F20x User Manual Figure 14-9. Data alignment of 12-bit resolution Figure 14-10. Data alignment of 10-bit resolution Figure 14-11. Data alignment of 8-bit resolution Regular group data Inserted group data Sign Sign Sign Sign DAL=0 Regular group data Inserted group data Sign DAL=1...
Page 264: Programmable Sample Time
GD32F20x User Manual Figure 14-12. Data alignment of 6-bit resolution 14.4.9. Programmable sample time The number of ADCCLK cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers. A different sample time can be specified for each channel.
Page 265: Dma Request
GD32F20x User Manual Table 14-4. External trigger for inserted channels for ADC0 and ADC1 ETSIC [2:0] Trigger Source Trigger Type TIMER0_TRGO TIMER0_CH3 TIMER1_TRGO Internal on-chip signal TIMER1_CH0 TIMER2_CH3 TIMER3_TRGO EXTI_15/TIMER7_CH3 External signal SWICST Software trigger Table 14-5. External trigger for regular channels for ADC2 ETSRC [2:0] Trigger Source Trigger Type...
Page 266: Temperature Sensor, And Internal Reference Voltage
GD32F20x User Manual 14.4.12. Temperature sensor, and internal reference voltage V REFINT When the TSVREN bit of ADC_CTL1 register is set, the temperature sensor channel (ADC0_CH16) and V channel (ADC0_CH17) is enabled. The temperature sensor can REFINT be used to measure the ambient temperature of the device. The sensor output voltage can be converted into a digital value by ADC.
Page 267: On-Chip Hardware Oversampling
GD32F20x User Manual Table 14-7. t timings depending on resolution CONV (min) CONV SMPL DRES [1:0] (ns) at (ADC (us) at f CONV (ADC clock (ADC clock bits = 28MHz clock cycles) 28MHz cycles) cycles) 12.5 446 ns 500 ns 10.5 375 ns 429 ns...
Page 268: Adc Sync Mode
GD32F20x User Manual are simply truncated. Figure 14-14. Numerical example with 5-bits shift and rounding shows a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 14-14. Numerical example with 5-bits shift and rounding Raw 20-bit data Final result after 5-bit shift and rounding to nearest...
Page 269 GD32F20x User Manual In ADC sync mode, the conversion starts alternately or simultaneously triggered by ADC0 master to ADC1 slave, according to the mode selected by the SYNCM[3:0] bits in ADC1_CTL0 register. In sync mode, when configure the conversion which is triggered by an external event, the slave ADC must be configured as triggered by the software in order to prevent false triggers to start unwanted conversion.
Page 270: Free Mode
GD32F20x User Manual Figure 14-15. ADC sync block diagram Regular Injected data registers （16 bits x 4） channels Regular data registers Inserted （16 bits） channels ADC1 (slave) ADC_IN0 Regular Injected data registers ADC_IN1 （16 bits x 4） GPIO channels ADC_IN15 Inserted Regular data registers SENSE...
Page 271: Inserted Parallel Mode
GD32F20x User Manual that will be sampled simultaneously by ACD0 and ADC1. Figure 14-16. Regular parallel mode on 16 channels 14.5.3. Inserted parallel mode This mode converts the inserted channel simultaneously. The source of external trigger comes from the inserted group MUX of ADC0 (selected by the ETSIC[2:0] bits in the ADC_CTL1 register).
Page 272: Follow-Up Slow Mode
GD32F20x User Manual of both ADCs are continuously converted. The behavior of follow-up fast mode shows in the Figure 14-18. Follow-up fast mode on 1 channel in continuous conversion mode. After an EOC interrupt is generated by ADC0 in case of setting the EOCIE bit, we can use a 32-bit DMA, which transfers to SRAM the ADC_RDATA 32-bit register containing the ADC1 converted data in the upper half word and the ADC0 converted data in the lower half word.
Page 273: Trigger Rotation Mode
GD32F20x User Manual Figure 14-19. Follow-up slow mode on 1 channel 14 ADCCLK 14 ADCCLK cycles cycles ADC0 · · · ADC1 · · · Regular trigger Sample EOC(ADC0 ) Convert EOC(ADC1) 14.5.6. Trigger rotation mode This mode can be running on the inserted channel group. The source of external trigger comes from the inserted channel MUX of ADC0 (selected by the ETSIC[2:0] bits in the ADC_CTL1 register).
Page 274: Combined Regular Parallel & Inserted Parallel Mode
GD32F20x User Manual ADC1 have been converted, the corresponded interrupt occurred. If another external trigger occurs after all inserted group channels have been converted then the trigger rotation process restarts. Figure 14-21. Trigger rotation: inserted channels in discontinuous mode 14.5.7. Combined regular parallel &...
Page 275: Combined Inserted Parallel & Follow-Up Mode
GD32F20x User Manual conversion, it will be ignored. Figure 14-23. Trigger occurs during inserted conversion shows the case (the third trigger is ignored). Figure 14-23. Trigger occurs during inserted conversion · · · ADC0 CH15 · · · ADC1 Sample CH14 this trigger is ignored Inserted...
Page 276: Register Definition
GD32F20x User Manual 14.7. Register definition ADC0 start address: 0x4001 2400 ADC1 start address: 0x4001 2800 ADC2 start address: 0x4001 3C00 14.7.1. Status register (ADC_STAT) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved STRC...
Page 277: Control Register 0 (Adc_Ctl0)
GD32F20x User Manual Cleared by software writing 0 to it or by reading the ADC_RDATA register. Analog watchdog event flag 0: No analog watchdog event 1: Analog watchdog event Set by hardware when the converted voltage crosses the values programmed in the ADC_WDLT and ADC_WDHT registers.
Page 278 GD32F20x User Manual Note: These bits are reserved in ADC1 and ADC2.In sync mode, the change of configuration will cause unpredictable consequences. We must disable sync mode before any configuration change. 15:13 DISNUM[2:0] Number of conversions in discontinuous mode The number of channels to be converted after a trigger will be DISNUM+1 DISIC Discontinuous mode on inserted channels 0: Discontinuous mode on inserted channels disable...
Page 279: Control Register 1 (Adc_Ctl1)
GD32F20x User Manual 01001: ADC channel 9 01010: ADC channel 10 01011: ADC channel 11 01100: ADC channel 12 01101: ADC channel 13 01110: ADC channel 14 01111: ADC channel15 10000: ADC channel16 10001: ADC channel17 Other values are reserved. Note: ADC0 analog inputs Channel16 and Channel17 are internally connected to the temperature sensor, and to V inputs.
Page 280 GD32F20x User Manual 0: External trigger for regular channel disable 1: External trigger for regular channel enable 19:17 ETSRC[2:0] External trigger select for regular channel For ADC0 and ADC1: 000: Timer 0 CH0 001: Timer 0 CH1 010: Timer 0 CH2 011: Timer 1 CH1 100: Timer 2 TRGO 101: Timer 3 CH3...
Page 281: Sample Time Register 0 (Adc_Sampt0)
GD32F20x User Manual 101: Timer 4 TRGO 110: Timer 4 CH3 111: SWICST Data alignment 0: LSB alignment 1: MSB alignment 10:9 Reserved Must be kept at reset value DMA request enable. 0: DMA request disable 1: DMA request enable Reserved Must be kept at reset value RSTCLB...
Page 282: Sample Time Register 1 (Adc_Sampt1)
GD32F20x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:21 SPT17[2:0] refer to SPT10[2:0] description 20:18 SPT16[2:0] refer to SPT10[2:0] description 17:15 SPT15[2:0] refer to SPT10[2:0] description 14:12 SPT14[2:0] refer to SPT10[2:0] description 11:9 SPT13[2:0] refer to SPT10[2:0] description SPT12[2:0] refer to SPT10[2:0] description...
Page 283: Inserted Channel Data Offset Register X (Adc_Ioffx) (X=0
GD32F20x User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value 29:27 SPT9[2:0] refer to SPT0[2:0] description 26:24 SPT8[2:0] refer to SPT0[2:0] description 23:21 SPT7[2:0] refer to SPT0[2:0] description 20:18 SPT6[2:0] refer to SPT0[2:0] description 17:15 SPT5[2:0] refer to SPT0[2:0] description 14:12 SPT4[2:0]...
Page 284: Watchdog High Threshold Register (Adc_Wdht)
GD32F20x User Manual These bits will be subtracted from the raw converted data when converting inserted channels. The conversion result can be read from in the ADC_IDATAx registers. 14.7.7. Watchdog high threshold register (ADC_WDHT) Address offset: 0x24 Reset value: 0x0000 0FFF This register has to be accessed by word(32-bit) Reserved Reserved...
Page 285: Regular Sequence Register 0 (Adc_Rsq0)
GD32F20x User Manual 14.7.9. Regular sequence register 0 (ADC_RSQ0) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RL[3:0] RSQ15[4:1] RSQ15[0] RSQ14[4:0] RSQ13[4:0] RSQ12[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:20 RL[3:0] Regular channel group length.
Page 286: Regular Sequence Register 2 (Adc_Rsq2)
GD32F20x User Manual 19:15 RSQ9[4:0] refer to RSQ0[4:0] description 14:10 RSQ8[4:0] refer to RSQ0[4:0] description RSQ7[4:0] refer to RSQ0[4:0] description RSQ6[4:0] refer to RSQ0[4:0] description 14.7.11. Regular sequence register 2 (ADC_RSQ2) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RSQ5[4:0] RSQ4[4:0]...
Page 287: Inserted Data Register X (Adc_Idatax) (X= 0
GD32F20x User Manual Reserved IL[1:0] ISQ3[4:1] ISQ3[0] ISQ2[4:0] ISQ1[4:0] ISQ0[4:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value 21:20 IL[1:0] Inserted channel group length. The total number of conversion in Inserted group equals to IL[1:0] + 1. 19:15 ISQ3[4:0] refer to ISQ0[4:0] description...
Page 288: Regular Data Register (Adc_Rdata)
GD32F20x User Manual These bits contain the number n conversion result, which is read only. 14.7.14. Regular data register (ADC_RDATA) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) ADC1RDTR[15:0] RDATA[15:0] Bits Fields Descriptions 31:16 ADC1RDTR[15:0] ADC1 regular channel data...
Page 289 GD32F20x User Manual 11: 6bit 11:10 Reserved Must be kept at reset value TOVS Triggered Oversampling This bit is set and cleared by software. 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio(OVSR[2:0]).
Page 290 GD32F20x User Manual conversion is ongoing).
Page 291: Digital-To-Analog Converter (Dac)
GD32F20x User Manual Digital-to-analog converter (DAC) 15.1. Overview The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 292: Function Overview
GD32F20x User Manual pins gives the pin description. Figure 15-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx TIMER5_TRGO TIMER2_TRGO TIMER6_TRGO TIMER4_TRGO TIMER1_TRGO TIMER3_TRGO EXTI_9 Buff SWTRx DAC_OUTx Control logic 12-bit 12-bit 12-bit Table 15-1. DAC pins Name Description Signal type Analog power supply Input, analog supply Ground for analog power supply...
Page 293: Dac Data Configuration
GD32F20x User Manual operational amplifier, an output buffer is integrated inside each DAC module. The output buffer, which is turned on by default, can be turned off by setting the DBOFFx bits in the DAC_CTL register. 15.3.3. DAC data configuration The 12-bit DAC holding data (DACx_DH) can be configured by writing any one of the DACx_R12DH, DACx_L12DH and DACx_R8DH registers.
Page 294: Dac Output Voltage
GD32F20x User Manual register. The amplitude of the noise can be configured by the DAC noise wave bit width (DWBWx) bits in the DAC_CTL register. There is a Linear Feedback Shift Register (LFSR) in the DAC control logic. In the LFSR noise mode, the LFSR noise signal is added to the DACx_DH value.
Page 295: Dma Request
GD32F20x User Manual 15.3.8. DMA request When the external trigger is enabled, the DMA request is enabled by setting the DDMAENx bits of the DAC_CTL register. A DAC DMA request will be generated when an external hardware trigger (not a software trigger) occurs. 15.3.9.
Page 296: Register Definition
GD32F20x User Manual 15.4. Register definition DAC start address: 0x4000 7400 15.4.1. Control register (DAC_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DDMAEN1 DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 Reserved DDMAEN0 DWBW0[3:0] DWM0[1:0] DTSEL0[2:0]...
Page 297 GD32F20x User Manual 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DAC1 trigger selection These bits select the external trigger of DAC1 when DTEN1=1. 000: Timer 5 TRGO 001: Timer 2 TRGO 010: Timer 6 TRGO 011: Timer 4 TRGO 100: Timer 1 TRGO 101: Timer 3 TRGO 110: EXTI line 9...
Page 298: Software Trigger Register (Dac_Swt)
GD32F20x User Manual ≥1011: The bit width of the wave signal is 12 DWM0[1:0] DAC0 noise wave mode These bits specify the mode selection of the noise wave signal of DAC0 when external trigger of DAC0 is enabled (DTEN0=1). 00: wave disabled 01: LFSR noise mode 1x: Triangle noise mode DTSEL0[2:0]...
Page 299: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value SWTR1 DAC1 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled 15.4.3.
Page 300: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32F20x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value 15.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH) Address offset: 0x10 Reset value: 0x0000 0000...
Page 301: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh)
GD32F20x User Manual These bits specify the data that is to be converted by DAC1. 15.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved Bits Fields...
Page 302: Dac Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh)
GD32F20x User Manual 15.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved DAC0_DH[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value 27:16 DAC1_DH[11:0] DAC1 12-bit right-aligned data...
Page 303: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32F20x User Manual 19:16 Reserved Must be kept at reset value 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value 15.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) Address offset: 0x28 Reset value: 0x0000 0000...
Page 304: Dac1 Data Output Register (Dac1_Do)
GD32F20x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 DAC0_DO [11:0] DAC0 data output These bits, which are read only, reflect the data that is being converted by DAC0. 15.4.13. DAC1 data output register (DAC1_DO) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 305: Watchdog Timer (Wdgt)
GD32F20x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 306: Figure 16-1. Free Watchdog Block Diagram
GD32F20x User Manual Figure 16-1. Free watchdog block diagram IRC40K The free watchdog is enabled by writing the value 0xCCCC in the control register (FWDGT_CTL), and the counter starts counting down. When the counter reaches the value 0x000, a reset is generated. The counter can be reloaded by writing the value 0xAAAA to the FWDGT_CTL register at anytime.
Page 307 GD32F20x User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1/128 13107.2 1/256 110 or 111 26214.4 The FWDGT timeout can be more accurate by calibrating the IRC40K.
Page 308: Register Definition
GD32F20x User Manual 16.1.4. Register definition FWDGT start address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMD[15:0]...
Page 309 GD32F20x User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1/4 001: 1/8 010: 1/16 011: 1/32 100: 1/64 101: 1/128 110: 1/256 111: 1/256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 310 GD32F20x User Manual Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid. This bit is reset by hardware after the update operation of FWDGT_RLD register.
Page 311: Window Watchdog Timer (Wwdgt)
GD32F20x User Manual 16.2. Window watchdog timer (WWDGT) 16.2.1. Overview The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of downcounter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit becomes cleared).
Page 312: Figure 16-2. Window Watchdog Timer Block Diagram
GD32F20x User Manual Figure 16-2. Window watchdog timer block diagram PCLK1/4096 Prescaler /1/2/4/8 7-Bit Down Counter CNT[6]=0 WDGTEN Reset CNT>WIN Reset Window WIN Write WWDGT_CTL The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register.
Page 313: Figure 16-3. Window Watchdog Timing Diagram
GD32F20x User Manual Figure 16-3. Window watchdog timing diagram Calculate the WWDGT timeout by using the formula below. × ( CNT [ 5:0 ] +1 ) (ms) ×4096 ×2 (16-1) WWDGT PCLK1 where: : WWDGT timeout WWDGT : APB1 clock period measured in ms PCLK1 Refer to the table below for the minimum and maximum values of the t WWDGT...
Page 314: Register Definition
GD32F20x User Manual 16.2.4. Register definition WWDGT start address:0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 315 GD32F20x User Manual counter is refreshed before it reaches the window value if the bit is set. It can be cleared by a hardware reset or by a RCU WWDGT software reset. A write operation of ‘0’ has no effect. PSC[1:0] Prescaler.
Page 316: Real-Time Clock(Rtc)
GD32F20x User Manual Real-time Clock(RTC) 17.1. Overview The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains, backup domain and VDD domain. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register.
Page 317: Rtc Reset
GD32F20x User Manual with the value of current system time. If alarm interrupt is enabled in the RTC_INTEN register, the RTC will generate an alarm interrupt when the system time equals to the alarm time (stored in the RTC_ALRMH/L register), Figure 17-1.
Page 318: Rtc Configuration
GD32F20x User Manual 17.3.3. RTC configuration The RTC_PSC, RTC_CNT and RTC_ALRM registers in the RTC core are writable. These registers’ value can be set only when the peripheral enter configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete.
Page 319 GD32F20x User Manual Figure 17-3. RTC second and overflow waveform example (RTC_PSC= 3)
Page 320: Register Definition
GD32F20x User Manual 17.4. Register definition RTC start address: 0x4000 2800 17.4.1. RTC interrupt enable register(RTC_INTEN) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions 31:3 Reserved...
Page 321: Rtc Prescaler High Register (Rtc_Psch)
GD32F20x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode.
Page 322: Rtc Prescaler Low Register(Rtc_Pscl)
GD32F20x User Manual 31:4 Reserved Must be kept at reset value PSC[19:16] RTC prescaler value high 17.4.4. RTC prescaler low register(RTC_PSCL) Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PSC[15:0] Bits Fields Descriptions...
Page 323: Rtc Counter High Register(Rtc_Cnth)
GD32F20x User Manual Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved DIV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated.
Page 324: Rtc Alarm High Register(Rtc_Alrmh)
GD32F20x User Manual Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] RTC counter value low 17.4.9. RTC alarm high register(RTC_ALRMH) Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits...
Page 325 GD32F20x User Manual 15:0 ALRM[15:0] RTC alarm value low...
Page 326: Timer
GD32F20x User Manual TIMER Table 18-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER1/2/3/4 TIMER8/11 TIMER9/10/12/13 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L2 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN, UP,DOWN, UP,DOWN, UP,DOWN, Count mode UP ONLY...
Page 327: Advanced Timer (Timerx, X=0, 7)
GD32F20x User Manual 18.1. Advanced timer (TIMERx, x=0, 7) 18.1.1. Overview The advanced timer module (Timer0 & Timer7) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 328: Block Diagram
GD32F20x User Manual  Daisy chaining of timer modules allows a single timer to initiate multiple timers.  Timer synchronization allows selected timers to start counting on the same clock cycle.  Timer Master/Slave mode controller. 18.1.3. Block diagram Figure 18-1. Advanced timer block diagram provides details of the internal configuration of...
Page 329 GD32F20x User Manual the advanced timer. Figure 18-1. Advanced timer block diagram...
Page 330: Function Overview
GD32F20x User Manual 18.1.4. Function overview Clock selection The advanced timer has the capability of being clocked by either the TIMER_CK or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal clock CK_TIMER is selected as timer clock source which is from module RCU.
Page 331: Figure 18-3. Counter Timing Diagram With Prescaler Division Change From 1 To
GD32F20x User Manual ITI0/1/2/3. This mode can be selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x0, 0x1, 0x2 or 0x3.  SMC1== 1’b1 ( ). External input is selected as timer clock source external clock mode 1 (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI.
Page 332: Figure 18-4. Up-Counter Timechart, Psc=0/1
GD32F20x User Manual counter reload value, the counter restarts from 0. If the repetition counter is set, the update events will be generated after (TIMERx_CREP+1) times of overflow. Otherwise the update event is generated each time when overflows. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode.
Page 333: Figure 18-5. Up-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-5. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set...
Page 334: Figure 18-6. Down-Counter Timechart, Psc=0/1
GD32F20x User Manual frequencies when TIMERx_CAR=0x63. Figure 18-6. Down-counter timechart, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) 5C 5B CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 335: Figure 18-7. Down-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-7. Down-counter timechart, change TIMERx_CAR on the go TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear...
Page 336: Figure 18-8. Center-Aligned Counter Timechart
GD32F20x User Manual prescaler register) are updated. Figure 18-8. Center-aligned counter timechart show some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0 Figure 18-8. Center-aligned counter timechart TIMER_CK CNT_CLK(PSC_CLK) …. …. …. CNT_REG Underflow Overflow UPIF TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 337: Figure 18-9. Repetition Timecart For Center-Aligned Counter
GD32F20x User Manual the counter was started. The update event generated at overflow when the CREP was written before starting the counter, and generated at underflow when the CREP was written after starting the counter. Figure 18-9. Repetition timecart for center-aligned counter TIMER_CK CNT_CLK ….
Page 338: Figure 18-11. Repetition Timechart For Down-Counter
GD32F20x User Manual Figure 18-11. Repetition timechart for down-counter TIMER_CK CNT_CLK …. …. …. …. …. CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Capture/compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 339: Figure 18-12. Input Capture Logic
GD32F20x User Manual Figure 18-12. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 340 GD32F20x User Manual and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 341: Figure 18-13. Output-Compare Under Three Modes
GD32F20x User Manual Figure 18-13. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 342 GD32F20x User Manual Figure 18-14. EAPWM timechart CHxVAL PWM MODE0 CHx OUT PWM MODE1 CHx OUT Interrupt signal CHxIF CHxOF Figure 18-15. CAPWM timechart CHxVAL PWM MODE0 CHx OUT PWM MODE1 CHx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF...
Page 343: Table 18-2. Complementary Outputs Controlled By Parameters
GD32F20x User Manual is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content. With regard to a more detail description refer to the relative bit definition.
Page 344 GD32F20x User Manual Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O = LOW CHx_ON=OxCPRE⊕CHxNP CHx_O output disable. CHx_ON output enable CHx_ON = LOW CHx_O=OxCPRE⊕ CHxP CHx_ON output disable. CHx_O output enable CHx_O=OxCPRE⊕ CHx_ON=(!OxCPRE)⊕ CHxP CHxNP CHx_O output enable CHx_ON output enable CHx_O = CHxP CHx_ON = CHxNP...
Page 345: Figure 18-16. Complementary Output With Dead-Time Insertion
GD32F20x User Manual dead-time insertion) Figure 18-16. Complementary output with dead-time insertion CHxVAL CxOPRE CHx_O CHx_ON Deadtime Corner case Deadtime > pulse width Pulse width CHx_O Deadtime CHx_ON Deadtime Break function In this function, the output CHx_O and CHx_ON are controlled by the POEN, IOS and ROS bits in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and cannot be set both to active level when break occurs.
Page 346: Figure 18-17. Output Behavior In Response To A Break (The Break High Active)
GD32F20x User Manual Figure 18-17. Output behavior in response to a break (The break high active) BRKIN OxCPRE = ISOx CHx_O CHxEN: 1 CHxNEN: 1 CHxP : 0 CHxNP : 0 ISOx = ~ISOxN = ISOxN CHx_ON = ISOx CHxEN: 1 CHxNEN: 0 CHx_O CHxP: 0 CHxNP : 0...
Page 347: Figure 18-18. Example Of Counter Operation In Encoder Interface Mode
GD32F20x User Manual Note:"-" means "no counting"; "X" means impossible. Figure 18-18. Example of counter operation in encoder interface mode Counter down Figure 18-19. Example of encoder interface mode with CI0FE0 polarity inverted Counter down Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 18-20.
Page 348 GD32F20x User Manual And TIMER_out needs to have functions of complementary and Dead-time, so only advanced timer can be chosen. In addition, based on the timers’ internal connection relationship, pair’s timers can be selected. For example: TIMER_in (TIMER0) -> TIMER_out (TIMER7 ITI0) TIMER_in (TIMER1) ->...
Page 349: Figure 18-21. Hall Sensor Timing Between Two Timers
GD32F20x User Manual Figure 18-21. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Slave controller The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 350: Figure 18-22. Restart Mode
GD32F20x User Manual Table 18-4. Slave mode example table Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0] LIST SMC[2:0] If you choose the CI0FE0 For the ITIx no filter and 000: ITI0 or CI1FE1, configure the prescaler can be used. 3'b100 (restart 001: ITI1 CHxP and CHxNP for the...
Page 351: Figure 18-23. Pause Mode
GD32F20x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection Figure 18-23. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF TRGS[2:0]=3’b1 Exam3 Event mode ETP = 0 no polarity ETPSC = 1, divided by 2. The counter will change. ETFC = 0 , no filter start to count ETIF is the when a rising...
Page 352: Figure 18-25. Single Pulse Mode, Timerx_Chxcv = 0X04, Timerx_Car=0X60
GD32F20x User Manual bit is written to 0 by software. If the CEN bit is cleared to 0 using software, the counter will be stopped and its value held. If the CEN bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized.
Page 353 GD32F20x User Manual Figure 18-26. Timer0 master/slave mode timer example TIMER0 TIMER 4 TRGS Master ITI0 TRG O Pre scaler Counter mode control TIMER 1 Master TRG O ITI1 Pre scaler Counter mode control TIMER 2 Master ITI2 TRG O Pre scaler Counter mode...
Page 354: Figure 18-27. Triggering Timer0 With Enable Signal Of Timer2
GD32F20x User Manual /3). Timer0’s SMC is set as 3 by the prescaler compared to TIMER_CK (f CNT_CLK TIMER_CK event mode, so Timer0 can not be disabled by Timer2’s disable signal. Do as follow: Configure Timer2 master mode to send its enable signal as trigger output(MMC=3’b001 in the TIMER2_CTL1 register) Configure Timer0 to select the input trigger from Timer2 (TRGS=3’b010 in the TIMERx_SMCFG register).
Page 355: Figure 18-28. Triggering Timer0 With Update Signal Of Timer2
GD32F20x User Manual Figure 18-28. Triggering TIMER0 with update signal of TIMER2 TIMER_CK CNT_REG software clear TRGIF hardware set CNT_REG  Enable Timer0 count with Timer2’s enable/O0CPRE signal In this example, we control the enable of Timer0 with the enable output of Timer2 .Refer to Figure 18-29.
Page 356: Figure 18-29. Pause Timer0 With Enable Signal Of Timer2
GD32F20x User Manual Figure 18-29. Pause TIMER0 with enable signal of TIMER2 TIMER_CK CNT_REG software clear software clear TRGIF CNT_REG In this example, we also can use O0CPRE as trigger source instead of enable signal output. Do as follow: Configure Timer2 in master mode and its output 0 Compare Prepare signal (O0CPRE) as trigger output (MMS=3’b100 in the TIMER2_CTL1 register).
Page 357: Figure 18-31. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32F20x User Manual We configure the start of Timer0 triggered by the enable signal of Timer2, and Timer2 is triggered by its CI0 input rises edge. To ensure 2 timers start synchronously, Timer2 must be configured in Master/Slave mode. Do as follow: Configure Timer2 in slave mode to get the input trigger from CI0 (TRGS=3’b100 in the TIMER2_SMCFG register).
Page 358 GD32F20x User Manual appointed by the field of DMATA in TIMERx_DMACFG. If the field of DMATC in TIMERx_DMACFG is 0(1 transfer), then the timer’s DMA request is finished. While if TIMERx_DMATC is not 0, such as 3( 4 transfers), then timer will send 3 more requests to DMA, and DMA will access timer’s registers DMATA+0x4, DMATA+0x8, DMATA+0xc at the next 3 accesses to TIMERx_DMATB.
Page 359: Register Definition
GD32F20x User Manual 18.1.5. Register definition TIMER0 start address: 0x4001 2C00 TIMER7 start address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields...
Page 360 GD32F20x User Manual 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when the counter is counting up and counting down, compare interrupt flag of channels can be set. After the counter is enabled, CAM[1:0] cannot be switched from 0x00 to non 0x00.
Page 361 GD32F20x User Manual This register has to be accessed by word(32-bit). Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output...
Page 362 GD32F20x User Manual case, the signal on TRGO is delayed compared to the actual reset. 001: Enable. This mode is useful to start several timers at the same time or to control a window in which a slave timer is enabled. In this mode the master mode controller selects the counter enable signal as TRGO.
Page 363 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge.
Page 364 GD32F20x User Manual 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6. SAMP 0111: f /4, N=8. SAMP 1000: f /8, N=6. SAMP 1001: f /8, N=8. SAMP 1010: f /16, N=5. SAMP 1011: f /16, N=6.
Page 365 GD32F20x User Manual 101: Pause mode. The trigger input enables the counter clock when it is high and disables the counter when it is low. 110: Event mode. A rising edge of the trigger input enables the counter. The counter cannot be disabled by the slave mode controller. 111: External clock mode 0.
Page 366 GD32F20x User Manual UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE...
Page 367 GD32F20x User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag Refer to CH0OF description CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag...
Page 368 GD32F20x User Manual Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs.
Page 369 GD32F20x User Manual set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1). 0: No affect 1: Generate channel’s c/c control update event Channel 3’s capture or compare event generation CH3G Refer to CH0G description Channel 2’s capture or compare event generation...
Page 370 GD32F20x User Manual Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL description CH1COMSEN Channel 1 output compare shadow enable Refer to CH0COMSEN description CH1COMFEN...
Page 371 GD32F20x User Manual 110: PWM mode0. When counting up, O0CPRE is high as long as the counter is smaller than TIMERx_CH0CV,otherwise it is low. When counting down, O0CPRE is low as long as the counter is larger than TIMERx_CH0CV, otherwise it is high. 111: PWM mode1.
Page 372 GD32F20x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control...
Page 373 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description...
Page 374 GD32F20x User Manual active level depends on CH2P and CH2NP bits. 000: Frozen. The O2CPRE signal keeps stable, independent of the comparison between the output compare register TIMERx_CH2CV and the counter TIMERx_CNT. 001: Set high on match. O2CPRE signal is forced high when the counter matches the output compare register TIMERx_CH2CV.
Page 375 GD32F20x User Manual This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH2EN bit in TIMERx_CHCTL2 register is reset).). 00: Channel 2 is configured as output 01: Channel 2 is configured as input, IS2 is connected to CI2FE2 10: Channel 2 is configured as input, IS2 is connected to CI3FE2 11: Channel 2 is configured as input, IS2 is connected to ITS.
Page 376 GD32F20x User Manual is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, capture is done on each channel input edge 01: Capture is done every 2 channel input edges 10: Capture is done every 4 channel input edges 11: Capture is done every 8 channel input edges CH2MS[1:0] Channel 2 mode selection...
Page 377 GD32F20x User Manual CH1P Channel 1 capture/compare function polarity Refer to CH0P description CH1EN Channel 1 capture/compare function enable Refer to CH0EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity.
Page 378 GD32F20x User Manual 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value.
Page 379 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000...
Page 380 GD32F20x User Manual CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 381 GD32F20x User Manual Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 382 GD32F20x User Manual Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. POEN Primary output enable This bit s set by software or automatically by hardware depending on the OAEN bit. It is cleared asynchronously by hardware as soon as the break input is active. When one of channels is configured in output mode, setting this bit enables the channel outputs (CHx_O and CHx_ON) if the corresponding enable bits (CHxEN, CHxNEN in TIMERx_CHCTL2 register) have been set.
Page 383 GD32F20x User Manual 10 or 11. Idle mode off-state configure When POEN bit is reset, this bit specifies the output state for the channels which has been configured in output mode. 0: When POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled.
Page 384 GD32F20x User Manual Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed is defined the number of DMA will access(R/W) the register of TIMERx_DMATB Reserved Must be kept at reset value.
Page 385 GD32F20x User Manual...
Page 386: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32F20x User Manual 18.2. General level0 timer (TIMERx, x=1, 2, 3, 4) 18.2.1. Overview The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 387 GD32F20x User Manual configuration of the general level0 timer. Figure 18-32. General Level 0 timer block diagram...
Page 388: Function Overview
GD32F20x User Manual 18.2.4. Function overview Clock selection The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when the slave mode is disabled (SMC [2:0] == 3’b000).
Page 389: Figure 18-34. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32F20x User Manual  SMC1== 1’b1 (external clock mode 1). External input pin source (ETI) The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 390: Figure 18-35. Up-Counter Timechart, Psc=0/1
GD32F20x User Manual If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled. When an update event occurs, all the registers (repetition counter, auto reload register, prescaler register) are updated. The following figures show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR=0x63.
Page 391: Figure 18-36. Up-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-36. Up-counter timechart, change TIMERx_CAR on the go. TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set...
Page 392: Figure 18-37. Down-Counter Timechart, Psc=0/1
GD32F20x User Manual Figure 18-37. Down-counter timechart, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) 5C 5B CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 18-38.
Page 393: Figure 18-39. Center-Aligned Counter Timechart
GD32F20x User Manual Center-aligned counting mode In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting mode and generates an underflow event when the counter counts to 1 in the down-counting mode.
Page 394 GD32F20x User Manual Figure 18-39. Center-aligned counter timechart TIMER_CK CNT_CLK(PSC_CLK) …. …. …. CNT_REG Underflow Overflow UPIF TIMERx_CTL0 CAM == 2'b11 CHxIF TIMERx_CTL0 CAM == 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM == 2'b01 (downcount only CHxIF Hardware set Software clear Capture/compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 395: Figure 18-40. Input Capture Logic
GD32F20x User Manual Figure 18-40. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 396 GD32F20x User Manual Result: When you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly.
Page 397: Figure 18-41. Output-Compare Under Three Modes
GD32F20x User Manual Figure 18-41. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 398 GD32F20x User Manual Figure 18-42. EAPWM timechart CHxVAL PWM MODE0 CHx OUT PWM MODE1 CHx OUT Interrupt signal CHxIF CHxOF Figure 18-43. CAPWM timechart CHxVAL PWM MODE0 CHx OUT PWM MODE1 CHx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF...
Page 399: Table 18-5. Counting Direction Versus Encoder Signals
GD32F20x User Manual The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 400: Figure 18-44. Example Of Counter Operation In Encoder Interface Mode
GD32F20x User Manual Figure 18-44. Example of counter operation in encoder interface mode Counter down Figure 18-45. Example of encoder interface mode with CI0FE0 polarity inverted Counter down Slave controller The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 401: Figure 18-46. Restart Mode
GD32F20x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection 110: CI1FE1 configure the ETP for For the ETIF, configure 111: ETIFP polarity selection Filter by ETFC and inversion. Prescaler by ETPSC. TRGS[2:0]=3’b Exam1 Restart mode ITI0, polarity For the ITI0, no filter The counter can be selector can be used.
Page 402: Figure 18-48. Event Mode
GD32F20x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0]=3’b Exam3 Event mode ETP = 0 no polarity ETPSC = 1, divided by The counter will start change. to count when a rising ETIF ETFC = 0 , no filter trigger input.
Page 403: Figure 18-49. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F20x User Manual Figure 18-49. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG …. O2CPRE Timers interconnection Refer to Advanced timer (TIMERx, x=0, Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB;...
Page 404: Register Definition
GD32F20x User Manual 18.2.5. Register definition TIMER1 start address: 0x4000 0000 TIMER2 start address: 0x4000 0400 TIMER3 start address: 0x4000 0800 TIMER4 start address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0]...
Page 405 GD32F20x User Manual center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Only when the counter is counting up, compare interrupt flag of channels can be set. 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register).
Page 406 GD32F20x User Manual Control register 1 (TIMERx_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input.
Page 407 GD32F20x User Manual DMAS DMA request source selection 0: DMA request of channel x is sent when channel x event occurs. 1: DMA request of channel x is sent when update event occurs. Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000...
Page 408 GD32F20x User Manual 11: ETI frequency will be divided by 8 11:8 ETFC[3:0] External trigger filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample ETI signal and the length of the digital filter applied to ETI.
Page 409 GD32F20x User Manual SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level.
Page 410 GD32F20x User Manual 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: disabled...
Page 411 GD32F20x User Manual Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 412 GD32F20x User Manual 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 413 GD32F20x User Manual flag was already high. 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
Page 414 GD32F20x User Manual 10: Channel 1 is configured as input, IS1 is connected to CI1FE1 11: Channel 1 is configured as input, IS1 is connected to ITS. This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register.
Page 415 GD32F20x User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 416 GD32F20x User Manual 0110: f /4, N=6 SAMP 0111: f /4, N=8 SAMP 1000: f /8, N=6 SAMP 1001: f /8, N=8 SAMP 1010: f /16, N=5 SAMP 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f...
Page 417 GD32F20x User Manual CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMSEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active.
Page 418 GD32F20x User Manual the comparison changes. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH2MS bit-filed is 00(COMPARE MODE). CH2COMSEN Channel 2 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH2CV register, which updates at each update event will be enabled.
Page 419 GD32F20x User Manual Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample CI2 input signal and the length of the digital filter applied to CI2.
Page 420 GD32F20x User Manual Bits Fields Descriptions 31:14 Reserved Must be kept at reset value CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description 11:10 Reserved Must be kept at reset value CH2P Channel 2 capture/compare function polarity Refer to CH0P description...
Page 421 GD32F20x User Manual This register has to be accessed by word(32-bit). Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000...
Page 422 GD32F20x User Manual CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 423 GD32F20x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 424 GD32F20x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 425 GD32F20x User Manual DMA transfer buffer register (TIMERx_DMATB) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed.
Page 426: General Level1 Timer (Timerx, X=8, 11)
GD32F20x User Manual 18.3. General level1 timer (TIMERx, x=8, 11) 18.3.1. Overview The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 427: Block Diagram
GD32F20x User Manual 18.3.3. Block diagram Figure 18-50. General level1 timer block diagram provides details on the internal configuration of the general level1 timer. Figure 18-50. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1 ITI2...
Page 428: Figure 18-51. Normal Mode, Internal Clock Divided By 1
GD32F20x User Manual Figure 18-51. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 ( ). External input pin source external clock mode 0 The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 429: Figure 18-52. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32F20x User Manual Figure 18-52. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK FA FB FC CNT_REG Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 430: Figure 18-53. Up-Counter Timechart, Psc=0/1
GD32F20x User Manual Figure 18-53. Up-counter timechart, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 18-54.
Page 431: Figure 18-55. Down-Counter Timechart, Psc=0/1
GD32F20x User Manual Down counting mode In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter restarts to count again from the counter-reload value. If the repetition counter is set, the update event will be generated after (TIMERx_CREP+1) times of underflow.
Page 432: Figure 18-56. Down-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-56. Down-counter timechart, change TIMERx_CAR on the go TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear...
Page 433: Figure 18-57. Center-Aligned Counter Timechart
GD32F20x User Manual prescaler register) are updated. Figure 18-57. Center-aligned counter timechart show some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0 Figure 18-57. Center-aligned counter timechart TIMER_CK CNT_CLK(PSC_CLK) …. …. …. CNT_REG Underflow Overflow UPIF TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 434: Figure 18-58. Input Capture Logic
GD32F20x User Manual CHxIE = 1. Figure 18-58. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1...
Page 435 GD32F20x User Manual Result: When you wanted input signal is got, TIMERx_CHxCV will be set by Counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly.
Page 436: Figure 18-59. Output-Compare Under Three Modes
GD32F20x User Manual Figure 18-59. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 437 GD32F20x User Manual Figure 18-60. EAPWM timechart CHxVAL PWM MODE0 CHx OUT PWM MODE1 CHx OUT Interrupt signal CHxIF CHxOF Figure 18-61. CAPWM timechart CHxVAL PWM MODE0 CHx OUT PWM MODE1 CHx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF...
Page 438: Table 18-7. Slave Controller Examples
GD32F20x User Manual level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content. With regard to a more detail description refer to the relative bit definition. Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04/0x05.
Page 439: Figure 18-62. Restart Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-62. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Exam2 Pause mode TI0S=0.（Non-xor） Filter is bypass in this TRGS[2:0]=3’b10 [CH0NP==0, CH0P==0] example. The counter can be no inverted.
Page 440: Figure 18-64. Event Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-64. Event mode TIMER_CK ETIFP CNT_REG TRGIF Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event automatically.
Page 441: Figure 18-65. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F20x User Manual Figure 18-65. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG …. O2CPRE Timers interconnection Refer to Advanced timer (TIMERx, x=0, Timer debug mode When the Cortex™-M3 halted, and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1, the TIMERx counter stops.
Page 442: Register Definition
GD32F20x User Manual 18.3.5. Register definition TIMER8 start address: 0x4001 4C00 TIMER11 start address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields...
Page 443 GD32F20x User Manual center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when the counter is counting up and counting down, compare interrupt flag of channels can be set. After the counter is enabled, CAM[1:0] cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down...
Page 444 GD32F20x User Manual This register has to be accessed by word(32-bit). Reserved Reserved TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 445 GD32F20x User Manual 110: Event mode. A rising edge of the trigger input enables the counter. The counter cannot be disabled by the slave mode controller. 111: External clock mode0. The counter counts on the rising edges of the selected trigger.
Page 446 GD32F20x User Manual Reserved Reserved CH1OF CH0OF Reserved TRGIF Reserved CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a...
Page 447 GD32F20x User Manual Reserved Reserved TRGG Reserved. CH1G CH0G Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
Page 448 GD32F20x User Manual CH1CO CH1CO CH0CO CH0CO CH1COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] MSEN MFEN MSEN MFEN CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 449 GD32F20x User Manual 010: Clear the channel output. O0CPRE signal is forced low when the counter matches the output compare register TIMERx_CH0CV. 011: Toggle on match. O0CPRE toggles when the counter matches the output compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced low level. 101: Force high.
Page 450 GD32F20x User Manual 11: Channel 0 is configured as input, IS0 is connected to ITS. This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register. Input capture mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 451 GD32F20x User Manual Same as Output compare mode Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CH1P CH1EN CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:6 Reserved Must be kept at reset value CH1P...
Page 452 GD32F20x User Manual [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CIxFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode. And CIxFE0 will be not inverted. CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state.
Page 453 GD32F20x User Manual 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 454 GD32F20x User Manual When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 455: General Level2 Timer (Timerx, X=9, 10, 12, 13)
GD32F20x User Manual 18.4. General level2 timer (TIMERx, x=9, 10, 12, 13) 18.4.1. Overview The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 456: Function Overview
GD32F20x User Manual Figure 18-66. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes Interrupt collector...
Page 457: Figure 18-67. Normal Mode, Internal Clock Divided By 1
GD32F20x User Manual Figure 18-67. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Prescaler The prescaler can divide the timer clock (TIMER_CK) to the counter clock (PSC_CLK by any factor between 1 and 65536.
Page 458: Figure 18-69. Up-Counter Timechart, Psc=0/1
GD32F20x User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts to count once again from 0. The update event is generated at each counter overflow.
Page 459: Figure 18-70. Up-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-70. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set...
Page 460: Figure 18-71. Down-Counter Timechart, Psc=0/1
GD32F20x User Manual The following figures show some examples of the counter behavior in different clock frequencies when TIMERx_CAR=0x63. Figure 18-71. Down-counter timechart, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) 5C 5B CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG...
Page 461: Figure 18-72. Down-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-72. Down-counter timechart, change TIMERx_CAR on the go TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear...
Page 462: Figure 18-73. Center-Aligned Counter Timechart
GD32F20x User Manual Figure 18-73. Center-aligned counter timechart show some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0 Figure 18-73. Center-aligned counter timechart TIMER_CK CNT_CLK(PSC_CLK) …. …. …. CNT_REG Underflow Overflow UPIF TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b01 (downcount only CHxIF...
Page 463: Figure 18-74. Input Capture Logic
GD32F20x User Manual Figure 18-74. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 464 GD32F20x User Manual Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 465: Figure 18-75. Output-Compare Under Three Modes
GD32F20x User Manual Figure 18-75. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Channel output reference signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 466 GD32F20x User Manual Timer debug mode When the Cortex™-M3 halted, and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1, the TIMERx counter stops.
Page 467: Register Definition
GD32F20x User Manual 18.4.5. Register definition TIMER9 start address: 0x4001 5000 TIMER10 start address: 0x4001 5400 TIMER12 start address: 0x4000 1C00 TIMER13 start address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0]...
Page 468 GD32F20x User Manual center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Only when the counter is counting up, compare interrupt flag of channels can be set. 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register).
Page 469 GD32F20x User Manual Control register 1 (TIMERx_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved MMC[2:0] Reserved Bits Fields Descriptions 31:7 Reserved Must be kept at reset value MMC[2:0] Master mode control These bits control the selection of TRGO signal, which is sent in master mode to slave timers for synchronization function.
Page 470 GD32F20x User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CH0IE UPIE Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE...
Page 471 GD32F20x User Manual 1: Over capture interrupt occurred Reserved Must be kept at reset value. Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs.
Page 472 GD32F20x User Manual 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved. CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions...
Page 473 GD32F20x User Manual This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00(COMPARE MODE). CH0COMSEN Channel 0 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0CV register, which updates at each update event, will be enabled.
Page 474 GD32F20x User Manual 0011: f , N=8 SAMP TIMER_CK 0100: f /2, N=6 SAMP 0101: f /2, N=8 SAMP 0110: f /4, N=6 SAMP 0111: f /4, N=8 SAMP 1000: f /8, N=6 SAMP 1001: f /8, N=8 SAMP 1010: f /16, N=5 SAMP 1011: f...
Page 475 GD32F20x User Manual 1: Channel 0 active low When channel 0 is configured in input mode, In conjunction with CH0P, this bit is used to define the polarity of CI0. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
Page 476 GD32F20x User Manual CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 477 GD32F20x User Manual 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 478: Basic Timer (Timerx, X=5, 6)
GD32F20x User Manual 18.5. Basic timer (TIMERx, x=5, 6) 18.5.1. Overview The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 479: Function Overview
GD32F20x User Manual 18.5.4. Function overview Clock selection The basic TIMER can only being clocked by the internal timer clock CK_TIMER, which is from the source named CK_TIMER in RCU The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler.
Page 480: Figure 18-78. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32F20x User Manual Figure 18-78. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK FA FB FC CNT_REG Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 481: Figure 18-79. Up-Counter Timechart, Psc=0/1
GD32F20x User Manual Figure 18-79. Up-counter timechart, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 18-80.
Page 482 GD32F20x User Manual Timer debug mode When the Cortex™-M3 halted, and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1, the TIMERx counter stops.
Page 483: Register Definition
GD32F20x User Manual 18.5.5. Register definition TIMER5 start address: 0x4000 1000 TIMER6 start address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions...
Page 484 GD32F20x User Manual –The slave mode controller generates an update event. 1: update event disable. The buffered registers keep their value, while the counter and the prescaler are reinitialized if the UG bit is set or if the slave mode controller generates a hardware reset event.
Page 485 GD32F20x User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 486 GD32F20x User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically.
Page 487 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 488: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32F20x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 19.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the peripheral clock (PCLK1 or PCLK2) to produce a dedicated baud rate lock for the USART transmitter and receiver.
Page 489: Function Overview
GD32F20x User Manual  ISO 7816-3 compliant smartcard interface – Character mode (T=0) – Block mode (T=1) – Direct and inverse convention  Multiprocessor communication – Enter into mute mode if address match does not occur – Wake up from mute mode by idle frame or address match detection ...
Page 490: Usart Frame Format
GD32F20x User Manual Figure 19-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controller Flow nCTS Controller USART Control Registers USART Address Transmitter Transimit clock...
Page 491: Baud Rate Generation
GD32F20x User Manual STB[1:0] stop bit length (bit) usage description Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame. A break frame is configured number of low bits followed by the configured number of stop bits.The transfer speed of a USART frame depends on the frequency of the PCLK, the configuration of the baud rate generator and the oversampling mode.
Page 492: Usart Receiver
GD32F20x User Manual The USART transmit procedure is shown in Figure 19-3. USART transmit procedure. The software can follow this flow: Set the UEN bit in USART_CTL0 to enable the USART. Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1 to configure the number of stop bits.
Page 493: Figure 19-4. Oversampling Method Of A Receive Frame Bit
GD32F20x User Manual Set the REN bit in USART_CTL0. After being enabled, the receiver receives a bit stream after a valid start pulse has been detected. Detection on noisy error, parity error, frame error and overrun error is performed during the reception of a frame. When a frame is received, the RBNE bit in USART_STAT0 is asserted, an interrupt is generated if the corresponding interrupt enable bit (RBNEIE) is set in the USART_CTL0 register.
Page 494: Use Dma For Data Buffer Access
GD32F20x User Manual 19.3.5. Use DMA for data buffer access To reduce the burden of the processor, DMA can be used to access the transmitting and receiving data buffer. The DENT bit in USART_CTL2 is used to enable the DMA transmission, and the DENR bit in USART_CTL2 is used to enable the DMA reception.
Page 495: Figure 19-6. Configuration Step When Using Dma For Usart Reception
GD32F20x User Manual NERR) in USART_STAT0. Figure 19-6. Configuration step when using DMA for USART reception Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 496: Figure 19-8. Hardware Flow Control
GD32F20x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full, and can be cleared by reading the USART_DATA register.
Page 497: Figure 19-9. Break Frame Occurs During Idle State
GD32F20x User Manual address flag is low, the frame is treated as a data frame. If the LSB 4 bits of an address frame are the same as the ADDR[3:0] bits in the USART_CTL1 register, the hardware clears the RWU bit and exits the mute mode. The RBNE bit is set for the frame that wakes up the USART. The status bits are available in the USART_STAT0 register.
Page 498: Figure 19-10. Break Frame Occurs During A Frame
GD32F20x User Manual during a frame on the RX pin, the FERR status will be asserted for the current frame. Figure 19-10. Break frame occurs during a frame frame1 frame0 frame2 RX pin 1 frame time FERR data0 data1 data2 USART_DATA LBDF 19.3.9.
Page 499: Figure 19-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32F20x User Manual Figure 19-12. 8-bit format USART synchronous waveform (CLEN=1) 19.3.10. IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be reset in IrDA mode.
Page 500: Figure 19-14. Irda Data Modulation
GD32F20x User Manual if the pulse width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block.
Page 501: Figure 19-15. Iso7816-3 Frame Format
GD32F20x User Manual be needed, which drives a bidirectional line that is also driven by the smartcard. The data frame consists of 1 start bit, 9 data bits (1 parity bit included) and 1.5 stop bits. The 0.5 stop bit may be configured for a receiver. Figure 19-15.
Page 502: Usart Interrupts
GD32F20x User Manual deactivate the NACK transmission. When requesting a read from the smartcard, the RT[23:0] bits in USART_RT register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. This timeout time is expressed in baudtime units. The RTF bit in USART_STAT1 will be asserted, if no answer is received from the card before the expiration of this period.
Page 503: Figure 19-16. Usart Interrupt Mapping Diagram
GD32F20x User Manual Table 19-3. USART interrupt requests Enable Interrupt event Event flag Control register Control bit Transmit data buffer empty USART_CTL0 TBEIE CTS toggled flag CTSF USART_CTL2 CTSIE Transmission complete USART_CTL0 TCIE Received buff not empty RBNE USART_CTL0 RBNEIE Overrun error ORERR Idle frame...
Page 504: Status Register 0 (Usart_Stat0)
GD32F20x User Manual USART1 start address: 0x4000 4400 USART2 start address: 0x4000 4800 USART5 start address: 0x4001 7000 UART3 start address: 0x4000 4C00 UART4 start address: 0x4000 5000 UART6 start address: 0x4000 7800 UART7 start address: 0x4000 7C00 19.4.1. Status register 0 (USART_STAT0) Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit)
Page 505 GD32F20x User Manual transmit shift register. An interrupt occurs if the TBEIE bit in USART_CTL0 is set. This bit is cleared when the software writes transmit data to the USART_DATA register. 0: Transmit data buffer is not empty 1: Transmit data buffer is empty Transmission complete This bit is set after power on.
Page 506: Data Register (Usart_Data)
GD32F20x User Manual FERR Frame error flag This bit is set when the RX pin is detected low during the stop bits of a receive frame. An interrupt occurs if the ERRIE bit in USART_CTL2 is set. Software can clear this bit by reading the USART_STAT0 and USART_DATA registers one by one.
Page 507: Control Register 0 (Usart_Ctl0)
GD32F20x User Manual This register has to be accessed by word (32-bit) Reserved INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept the reset value 15:4 INTDIV[11:0] Integer part of baud-rate divider FRADIV[3:0] Fraction part of baud-rate divider 19.4.4.
Page 508 GD32F20x User Manual 0: Parity check function disabled 1: Parity check function enabled This bit field cannot be written when the USART is enabled (UEN=1). Parity mode 0: Even parity 1: Odd parity This bit field cannot be written when the USART is enabled (UEN=1). PERRIE Parity error interrupt enable.
Page 509: Control Register 1 (Usart_Ctl1)
GD32F20x User Manual set by hardware when the USART receives an address mismatch frame. 0: Receiver in active mode 1: Receiver in mute mode SBKCMD Send break command Software can set this bit to send a break frame. Hardware resets this bit automatically when the break frame has been transmitted. 0: Do not transmit a break frame 1: Transmit a break frame 19.4.5.
Page 510: Control Register 2 (Usart_Ctl2)
GD32F20x User Manual CK polarity This bit specifies the polarity of the CK pin in synchronous mode. 0: The CK pin is in low state when the USART is in idle state 1: The CK pin is in high state when the USART is in idle state This bit field cannot be written when the USART is enabled (UEN=1).
Page 511 GD32F20x User Manual Reserved Reserved CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields Descriptions 31:11 Reserved Must be kept the reset value CTSIE CTS interrupt enable If this bit is set, an interrupt occurs when the CTSF bit in USART_STAT0 is set. 0: CTS interrupt is disabled 1: CTS interrupt is enabled This bit is reserved for UART3/4/6/7.
Page 512: Guard Time And Prescaler Register (Usart_Gp)
GD32F20x User Manual 1: Enable NACK transmission This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved for UART3/4/6/7. HDEN Half-duplex enable This bit enables the half-duplex USART mode. 0: Half duplex mode is disabled 1: Half duplex mode is enabled This bit field cannot be written when the USART is enabled (UEN=1).
Page 513: Control Register 3 (Usart_Ctl3)
GD32F20x User Manual 15:8 GUAT[7:0] Guard time value in Smartcard mode TC flag assertion time is delayed by GUAT[7:0] baud clock cycles. This bit field cannot be written when the USART is enabled (UEN=1). These bits are not available for UART3/4/6/7. PSC[7:0] When the USART IrDA low-power mode is enabled, these bits specify the division factor that is used to divide the peripheral clock (PCLK1/PCLK2) to generate the...
Page 514 GD32F20x User Manual 1: data is transmitted/received with the MSB first This bit field cannot be written when the USART is enabled (UEN=1). DINV Data bit level inversion This bit specifies the polarity of the data bits in transmission and reception. 0: Data bit signal values are not inverted 1: Data bit signal values are inverted This bit field cannot be written when the USART is enabled (UEN=1).
Page 515: Receiver Timeout Register (Usart_Rt)
GD32F20x User Manual 19.4.9. Receiver timeout register (USART_RT) Address offset: 0x84 Reset value: 0x0000 0000 This register is not available for UART3/4/6/7. This register has to be accessed by word (32-bit) BL[7:0] RT[23:16] RT[15:0] Bits Fields Descriptions 31:24 BL[7:0] Block Length These bits specify the block length in Smartcard T=1 reception.
Page 516 GD32F20x User Manual Reserved Reserved Reserved Bits Fields Descriptions 31:17 Reserved Must be kept the reset value Busy flag This bit is set when the USART is receiving a data frame. 0: USART reception path is idle 1: USART reception path is working 15:13 Reserved Must be kept the reset value...
Page 517: Figure 20-1. I2C Module Block Diagram
GD32F20x User Manual Inter-integrated circuit interface (I2C) 20.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. with standard-mode and fast-mode The I2C interface implements standard I2C protocol well as CRC calculation and checking, SMBus (system management bus) and PMBus (power...
Page 518: Table 20-1. Definition Of I2C-Bus Terminology
GD32F20x User Manual Figure 20-1. I2C module block diagram PEC register CRC Calculation / Check Noise SDA Controller Shift Register filter Noise SCL Controller filter Data Register Control Registers SMBA Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 20-1. Definition of I2C-bus terminology (refre to the I2C specification of philips semiconductors) Term Description...
Page 519: Figure 20-2. Data Validation
GD32F20x User Manual current-source or pull-up resistor. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collect to perform the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the standard-mode and up to 400 kbit/s in the fast-mode.
Page 520: Figure 20-4. Clock Synchronization
GD32F20x User Manual is done by clock synchronization and bus arbitration. In a single master system, clock synchronization and bus arbitration are unnecessary. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line causes the masters concerned to start counting off their LOW period and, once a master clock has gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see Figure 20-4.
Page 521: Figure 20-6. I2C Communication Flow With 7-Bit Address
GD32F20x User Manual 20.3.6. I2C communication flow Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. An I2C slave will continue to detect addresses after a START condition on I2C bus and compare the detected address with its slave address which is programmable by software.
Page 522 GD32F20x User Manual  Master Receiver  Slave Transmitter  Slave Receiver I2C block supports all of the four I2C modes. After system reset, it works in slave mode. If it’s programmed by software and finished sending a START condition on I2C bus, it changes into master mode.
Page 523 GD32F20x User Manual clears AERR bit by writing 0 to it.
Page 524: Figure 20-9. Programming Model For Slave Transmitting
GD32F20x User Manual Figure 20-9. Programming model for slave transmitting I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND START condition Master sends header...
Page 525: Figure 20-10. Programming Model For Slave Receiving
GD32F20x User Manual As soon as the first byte is received, RBNE is set by hardware. Software can now read the first byte from I2C_DATA and RBNE is cleared as well. Any time RBNE is set, software can read a byte from I2C_DATA. After last byte is received, RBNE is set.
Page 526 GD32F20x User Manual register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If the address sent is a header of 10-bit address, the hardware sets ADD10S END bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA.
Page 527: Figure 20-11. Programming Model For Master Transmitting
GD32F20x User Manual Figure 20-11. Programming model for master transmitting I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 528 GD32F20x User Manual Software set START bit requesting I2C to generate a START condition to I2C bus. After sending a START condition, the I2C hardware sets the SBSEND bit in I2C status register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA.
Page 529: Figure 20-12. Programming Model For Master Receiving Using Solution A
GD32F20x User Manual Figure 20-12. Programming model for master receiving using Solution A Hardware I2C Line State Software Flow Action 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND...
Page 530 GD32F20x User Manual I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If the address sent is a header of 10-bit address, the hardware sets ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address toI2C_DATA.
Page 531: Figure 20-13. Programming Model For Master Receiving Using Solution B
GD32F20x User Manual Figure 20-13. Programming model for master receiving using solution B I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND...
Page 532: Packet Error Checking
GD32F20x User Manual write or read a byte, this may cause CPU’s high overload. The DMA controller can be used to process TBE and RBNE flag: each time TBE or RBNE is asserted, DMA controller does a read or write operation automatically. The DMA request is enabled by the DMAON bit in the I2C_CTL1 register.
Page 533 GD32F20x User Manual Address resolution protocol The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’...
Page 534: Table 20-2. Event Status Flags
GD32F20x User Manual In order to support address resolution protocol (ARP) (ARPEN=1), the software should response to HSTSMB flag in SMBus Host Mode (SMBTYPE =1) or DEFSMB flag in SMBus Device Mode, and implement the function of ARP protocol. In order to support SMBus Alert Mode, the software should response to SMBALT flag and implement the related function.
Page 535: Register Definition
GD32F20x User Manual 20.4. Register definition I2C0 start address: 0x4000 5400 I2C1 start address: 0x4000 5800 I2C2 start address: 0x4000 C000 20.4.1. Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) SRESET Reserved SALT PECTRANS...
Page 536 GD32F20x User Manual byte ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0 0: ACK will not be sent 1: ACK will be sent STOP Generate a STOP condition on I2C bus This bit is set and cleared by software and set by hardware when SMBUs timeout and cleared by hardware when STOP condition detected.
Page 537: Control Register 1 (I2C_Ctl1)
GD32F20x User Manual 20.4.2. Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word (32-bit) Reserved DMALST DMAON BUFIE EVIE ERRIE Reserved I2CCLK[5:0] Bits Fields Descriptions 15:13 Reserved Must be kept the reset value DMALST Flag indicating DMA last transfer 0: Next DMA EOT is not the last transfer...
Page 538: Slave Address Register 0 (I2C_Saddr0)
GD32F20x User Manual 8MHz. In I2C fast mode plus, the frequencies of APB1 must be equal or greater than 24MHz. 20.4.3. Slave address register 0 (I2C_SADDR0) Address offset: 0x08 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) ADDFORM Reserved ADDRESS[9:8]...
Page 539: Transfer Buffer Register (I2C_Data)
GD32F20x User Manual 20.4.5. Transfer buffer register (I2C_DATA) Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved TRB[7:0] Bits Fields Descriptions 15:8 Reserved Must be kept the reset value TRB[7:0] Transmission or reception data buffer 20.4.6.
Page 540 GD32F20x User Manual OUERR Over-run or under-run situation occurs in slave mode, when SCL stretching is disabled. In slave receiving mode, if the last byte in I2C_DATA is not read out while the following byte is already received, over-run occurs. In slave transmitting mode, if the current byte is already sent out, while the I2C_DATA is still empty, under-run occurs.
Page 541: Transfer Status Register 1 (I2C_Stat1)
GD32F20x User Manual This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA. 0: No header of 10-bit address sent in master mode 1: Header of 10-bit address is sent in master mode Byte transmission completed. If a byte is already received in shift register but I2C_DATA is still full in receiving mode or a byte is already sent out from shift register but I2C_DATA is still empty in transmitting mode, the BTC flag is asserted.
Page 542: Clock Configure Register (I2C_Ckcfg)
GD32F20x User Manual 0: SADDR0 address matches 1: SADDR1 address matches HSTSMB SMBus Host Header detected in slave mode This bit is cleared by hardware after a STOP or a START condition or I2CEN=0 0: No SMBus Host Header detected 1: SMBus Host Header detected DEFSMB Default address of SMBusDevice...
Page 543: Rise Time Register (I2C_Rt)
GD32F20x User Manual FAST I2C speed selection in master mode 0: Standard speed 1: Fast speed DTCY Duty cycle in fast mode high 1: T = 16/9 high 13:12 Reserved Must be kept the reset value 11:0 CLKC[11:0] I2C Clock control in master mode In standard speed mode: T = CLKC ∗...
Page 544: Serial Peripheral Interface/Inter-Ic Sound (Spi/I2S)
GD32F20x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 21.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 545: Figure 21-1. Block Diagram Of Spi
GD32F20x User Manual  Master clock (MCK) can be output.  Transmission and reception using DMA. 21.3. SPI block diagram Figure 21-1. Block diagram of SPI SYSCLK Clock Generator Control Registers TxRx Control Logic MOSI TX Buffer MISO Shift Register RX Buffer 21.4.
Page 546: Table 21-2. Quad-Spi Signal Description
GD32F20x User Manual Pin Name Direction Description single master or (NSSDRV=0) for multi-master application. Slave in Hardware NSS Mode: NSS input, as a chip select signal for slave. 21.4.2. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0).
Page 547: Figure 21-2. Spi Timing Diagram In Normal Mode
GD32F20x User Manual Figure 21-2. SPI timing diagram in normal mode Figure 21-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) MOSI D[4] D[0] D[4] D[0] MISO D[5] D[1] D[5] D[1] D[6] D[2] D[6] D[2] D[7] D[3] D[7] D[3] NSS(slave) Capture In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register.
Page 548: Table 21-3. Spi Operation Modes
GD32F20x User Manual Master mode In master mode (MSTMOD=1) if the application uses multi-master connection, NSS can be configured to hardware input mode (SWNSSEN=0, NSSDRV=0) or software mode (SWNSSEN=1). Then, once the NSS pin (in hardware NSS mode) or the SWNSS bit (in software NSS mode) goes low, the SPI automatically enters to slave mode and triggers a master fault flag CONFERR.
Page 549: Figure 21-4. A Typical Full-Duplex Connection
GD32F20x User Manual Mode Description Register Configuration Data Pin Usage unidirectional connection RO = 0 MISO: Transmission BDEN = 0 BDOEN: Don’t care MSTMOD = 0 Slave Reception with RO = 1 MOSI: Reception unidirectional connection BDEN = 0 MISO: Not used BDOEN: Don’t care MSTMOD = 0 Slave Transmission with...
Page 550: Figure 21-6. A Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
GD32F20x User Manual Figure 21-6. A typical simplex connection (Master: Transmit only, Slave: Receive) Figure 21-7. A typical bidirectional connection SPI initialization sequence Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate, otherwise, ignore this step.
Page 551 GD32F20x User Manual SPI basic transmission and reception sequence Transmission sequence After the initialization sequence, the SPI is enabled and stays at idle state. In master mode, the transmission starts when the application writes a data into the transmit buffer. In slave mode the transmission starts when SCK clock signal begins to toggle at SCK pin and NSS level is low, so application should ensure that data is already written into transmit buffer before the transmission starts in slave mode.
Page 552 GD32F20x User Manual Quad-SPI mode operation sequence The Quad-SPI mode is designed to control quad SPI flash. In order to enter Quad-SPI mode, the software should first verify that the TBE bit is set and TRANS bit is cleared, then set QMOD bit in SPI_QCTL register. In Quad-SPI mode, BDEN, BDOEN, CRCEN, CRCNT, FF16, RO and LF in SPI_CTL0 register should be kept cleared and MSTMOD should be set to ensure that SPI is in master mode.
Page 553: Figure 21-8. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32F20x User Manual Figure 21-8. Timing diagram of quad write operation in Quad-SPI mode Software Write Hadware Sets TBE again SPI_DATA MOSI D1[4] D1[0] D2[4] D2[0] MISO D1[5] D1[1] D2[5] D2[1] D1[6] D1[2] D2[6] D2[2] D1[7] D1[3] D2[7] D2[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 554: Figure 21-9. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32F20x User Manual Figure 21-9. Timing diagram of quad read operation in Quad-SPI mode Software Writes Hadware Sets TBE SPI_DATA Software Writes SPI_DATA Software Reads SPI_DATA RBNE MOSI D1[4] D1[0] D2[4] D2[0] MISO D1[5] D1[1] D2[5] D2[1] D1[6] D1[2] D2[6] D2[2] D1[7] D1[3]...
Page 555: Dma Function
GD32F20x User Manual TRANS=0 to ensure the on-going transfer completes. Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that, TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared.
Page 556: Table 21-4. Spi Interrupt Requests
GD32F20x User Manual This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register.  Receive buffer not empty flag (RBNE) This bit is set when receive buffer is not empty, which means that one data is received and stored in the receive buffer, and software can read the data by reading the SPI_DATA register.
Page 557: Figure 21-10. Block Diagram Of I2S
GD32F20x User Manual Interrupt Flag Description Clear Method Enable bit Read SPI_DATA register, then RXORERR Rx Overrun Error read SPI_STAT register. CRCERR CRC error Write 0 to CRCERR bit 21.7. I2S block diagram Figure 21-10. Block diagram of I2S SYSCLK I2S_MCK Control Clock Generator...
Page 558: Figure 21-11. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F20x User Manual 21.9. I2S function overview 21.9.1. I2S audio standards The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTL register. Four audio standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified standard, and PCM standard. All standards except PCM handle audio data time-multiplexed on two channels (the left channel and the right channel).
Page 559: Figure 21-13. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32F20x User Manual to or from the SPI_DATA register is needed to complete a frame. Figure 21-13. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 21-14. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) When the packet type is 32-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 560: Figure 21-17. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F20x User Manual Figure 21-17. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 21-18. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete a frame.
Page 561: Figure 21-22. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F20x User Manual Figure 21-22. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 21-23. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 21-24. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 21-25. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) 16-bit data...
Page 562: Figure 21-27. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F20x User Manual Figure 21-27. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 21-28. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 563: Figure 21-31. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F20x User Manual handled in the exactly same way as that for I2S Phillips standard. The timing diagrams for each configuration of the short frame synchronization mode are shown below. Figure 21-31. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=0) Figure 21-32.
Page 564: Figure 21-37. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F20x User Manual (DTLEN=01, CHLEN=1, CKPL=1) Figure 21-37. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 21-38. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 16-bit data 16-bit 0 The timing diagrams for each configuration of the long frame synchronization mode are shown below.
Page 565: Figure 21-42. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F20x User Manual (DTLEN=10, CHLEN=1, CKPL=0) Figure 21-42. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 21-43. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 13 bits 24-bit data 8-bit 0 Figure 21-44.
Page 566: Figure 21-47. Block Diagram Of I2S Clock Generator
GD32F20x User Manual 21.9.2. I2S clock Figure 21-47. Block diagram of I2S clock generator The block diagram of I2S clock generator is shown as Figure 21-47. Block diagram of I2S clock generator. The I2S interface clocks are configured by the DIV bits, the OF bit, the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register.
Page 567: Table 21-7. Direction Of I2S Interface Signals For Each Operation Mode
GD32F20x User Manual precision demand, an external precise I2S clock can be imported from I2S_CKIN pin. 21.9.3. Operation Operation modes The operation mode is selected by the I2SOPMOD bits in the SPI_I2SCTL register. There are four available operation modes, including master transmission mode, master reception mode, slave transmission mode, and slave reception mode.
Page 568 GD32F20x User Manual I2S master transmission sequence The TBE flag is used to control the transmission sequence. As is mentioned before, the TBE flag indicates that the transmit buffer is empty, and an interrupt will be generated if the TBEIE bit in the SPI_CTL1 register is set.
Page 569 GD32F20x User Manual 1, and I2SSTD = 10) Wait for the second last RBNE Then wait 17 I2S CK clock (clock on I2S_CK pin) cycles Clear the I2SEN bit  16-bit data packed in 32-bit frame in the audio standards except the LSB justified standard (DTLEN = 00, CHLEN = 1, and I2SSTD is not equal to 10) Wait for the last RBNE Then wait one I2S clock cycle...
Page 570: Dma Function
GD32F20x User Manual In order to switch off I2S, it is mandatory to clear the I2SEN bit immediately after receiving the last RBNE. 21.9.4. DMA function DMA function is the same as SPI mode. The only difference is that the CRC function is not available in I2S mode.
Page 571: Table 21-8. I2S Interrupt
GD32F20x User Manual newly incoming data is lost. I2S interrupt events and corresponding enabled bits are summed up in the Table 21-8. I2S interrupt. Table 21-8. I2S interrupt Interrupt Flag Name Description Clear Method Enable bit Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty...
Page 572: Register Definition
GD32F20x User Manual 21.11. Register definition SPI0 start address: 0x4001 3000 SPI1 start address: 0x4000 3800 SPI2 start address: 0x4000 3C00 21.11.1. Control register 0 (SPI_CTL0) Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word (32-bit) This register has no meaning in I2S mode.
Page 573 GD32F20x User Manual received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex 1: Receive-only SWNSSEN NSS Software Mode Selection 0: NSS hardware mode.
Page 574: Control Register 1 (Spi_Ctl1)
GD32F20x User Manual 21.11.2. Control register 1 (SPI_CTL1) Address offset: 0x04 Reset value: 0x0000 This register has to be accessed by word (32-bit) Reserved Reserved TBEIE RBNEIE ERRIE Reserved NSSDRV DMATEN DMAREN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TBEIE Transmit Buffer Empty Interrupt Enable 0: TBE interrupt is disabled.
Page 575: Status Register (Spi_Stat)
GD32F20x User Manual a DMA request at corresponding DMA channel. 21.11.3. Status register (SPI_STAT) Address offset: 0x08 Reset value: 0x0002 This register has to be accessed by word(32-bit). Reserved Reserved TRANS RXORERR CONFERR CRCERR TXURERR I2SCH RBNE rc_w0 Bits Fields Descriptions 31:8 Reserved...
Page 576: Data Register (Spi_Data)
GD32F20x User Manual This bit is set by hardware and cleared by a read operation on the SPI_STAT register. This bit is not used in SPI mode. I2SCH I2S channel side 0: The next data needs to be transmitted or the data just received belongs to left channel.
Page 577: Crc Polynomial Register (Spi_Crcpoly)
GD32F20x User Manual 21.11.5. CRC polynomial register (SPI_CRCPOLY) Address offset: 0x10 Reset value: 0x0007 This register has to be accessed by word(32-bit), Reserved CPR [15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CPR[15:0] CRC polynomial register This register contains the CRC polynomial and it is used for CRC calculation.
Page 578: Tx Crc Register (Spi_Tcrc)
GD32F20x User Manual This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit reset in RCU register is set. 21.11.7. TX CRC register (SPI_TCRC) Address offset: 0x18 Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved TCR[15:0] Bits...
Page 579 GD32F20x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value I2SSEL I2S mode selection 0: SPI mode 1: I2S mode This bit should be configured when SPI mode or I2S mode is disabled. I2SEN I2S enable 0: I2S is disabled 1: I2S is enabled This bit is not used in SPI mode.
Page 580: I2S Clock Prescaler Register (Spi_I2Spsc)
GD32F20x User Manual 11: Reserved These bits should be configured when I2S mode is disabled. These bits are not used in SPI mode. CHLEN Channel length 0: 16 bits 1: 32 bits The channel length must be equal to or greater than the data length. This bit should be configured when I2S mode is disabled.
Page 581: Quad-Spi Mode Control Register (Spi_Qctl) Of Spi0
GD32F20x User Manual 21.11.10. Quad-SPI mode control register (SPI_QCTL) of SPI0 Address offset: 0x80 Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved Reserved IO23_DRV QMOD Bits Fields Descriptions 31:3 Reserved Must be kept at reset value IO23_DRV Drive IO2 and IO3 enable 0: IO2 and IO3 are not driven in single wire mode...
Page 582: Figure 22-1. Dci Module Block Diagram
GD32F20x User Manual Digital camera interface(DCI) 22.1. Overview DCI is a parallel interface to capture video or picture from a camera. It supports various color space such as YUV/RGB, as well as compression format such as JPEG. 22.2. Characteristics  Digital video/picture capture ...
Page 583: Figure 22-2. Hardware Synchronization Mode
GD32F20x User Manual mode. In DCI embedded synchronization mode, video synchronization information is embedded into pixel data and there is no hardware horizontal or vertical synchronization signal (DCI_Hs or DCI_Vs). DCI uses embedded sync detection module to extract synchronization information from pixel data, and then recover horizontal and vertical synchronization signals.
Page 584: Figure 22-3. Hardware Synchronization Mode: Jpeg Format Supporting
GD32F20x User Manual JPEG mode DCI supports JPEG video/picture compression format in hardware synchronization mode. In JPEG mode (JM bit in DCI_CTL is set), the DCI_Vs is used to indicate start of a new frame, and DCI_Hs is used as stream data valid signal. Figure 22-3.
Page 585: Table 22-2. Memory View In Byte Padding Mode
GD32F20x User Manual The DCI capture frequency is defined by FR[1:0] bits in continuous mode. For example, if FR[1:0]=00, DCI captures each frame, and if FR[1:0]=01, DCI only captures every alternate frame. In continuous mode, software may clear the CAP bit any time when DCI is capturing data, but DCI doesn’t stop capture immediately.
Page 586: Table 22-3. Memory View In Half-Word Padding Mode
GD32F20x User Manual Half-word padding mode Half-word padding is used if data width of DCI interface is configured into 10/12/14. In this mode each pixel data is extended into 16-bits length by filling zero at higher position, so the 32-bits width data buffer is able to hold two pixel data. DCI pushes the data buffer into pixel FIFO each time the buffer is full or line end.
Page 587: Register Definition
GD32F20x User Manual 22.7. Register definition DCI start address: 0x5005 0000 22.7.1. Control register (DCI_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved DCIEN Reserved DCIF[1:0] FR[1:0] WDEN SNAP Bits Fields Descriptions 31:15...
Page 588: Status Register0 (Dci_Stat0)
GD32F20x User Manual Clock Polarity Selection 0: Capture at falling edge 1: Capture at rising edge Embedded Synchronous Mode 0: Embedded synchronous mode is disabled 1: Embedded synchronous mode is enabled JPEG Mode 0: JPEG mode is disabled 1: JPEG mode is enabled WDEN Window Enable 0: Window is disabled...
Page 589: Status Register1 (Dci_Stat1)
GD32F20x User Manual HS line status 0: Not in horizontal blanking period 1: In horizontal blanking period 22.7.3. Status register1 (DCI_STAT1) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ESEF OVRF Bits Fields...
Page 590: Interrupt Flag Register (Dci_Intf)
GD32F20x User Manual Reserved Reserved ELIE VSIE ESEIE OVRIE EFIE Bits Fields Descriptions 31:5 Reserved Must keep the reset value ELIE End of Line Interrupt Enable 0: End of line flag won’t generate interrupt 1: End of line flag will generate interrupt VSIE Vsync Interrupt Enable 0: Vsync flag won’t generate interrupt...
Page 591: Interrupt Flag Clear Register (Dci_Intc)
GD32F20x User Manual Bits Fields Descriptions 31:5 Reserved Must keep the reset value ELIF End of Line Interrupt Flag VSIF Vsync Interrupt Flag ESEIF Embedded Synchronous Error Interrupt Flag OVRIF FIFO Overrun Interrupt Flag EFIF End of Frame Interrupt Flag 22.7.6.
Page 592: Synchronization Codes Unmask Register (Dci_Scumsk)
GD32F20x User Manual This register has to be accessed by word (32-bit) FE[7:0] LE[7:0] LS[7:0] FS[7:0] Bits Fields Descriptions 31:24 FE[7:0] Frame End Code in Embedded Synchronous Mode 23:16 LE[7:0] Line End Code in Embedded Synchronous Mode 15:8 LS[7:0] Line Start Code in Embedded Synchronous Mode FS[7:0] Frame Start Code in Embedded Synchronous Mode 22.7.8.
Page 593: Cropping Window Size Register (Dci_Cwsz)
GD32F20x User Manual Reserved WVSP[12:0] Reserved WHSP[13:0] Bits Fields Descriptions 31:29 Reserved Must keep the reset value 28:16 WVSP[12:0] Window Vertical Start Position Zero means the first line 15:14 Reserved Must keep the reset value 13:0 WHSP[13:0] Window Horizontal Start Position Zero means the first pixel in a line 22.7.10.
Page 594 GD32F20x User Manual This register has to be accessed by word (32-bit) DT3[[7:0] DT2[7:0] DT1[7:0] DT0[7:0] Bits Fields Descriptions 31:24 DT3[7:0] Pixel Data 3 23:16 DT2[7:0] Pixel Data 2 15:8 DT1[7:0] Pixel Data 1 DT0[7:0] Pixel Data 0...
Page 595: Tft-Lcd Interface (Tli)
GD32F20x User Manual TFT-LCD interface (TLI) 23.1. Overview The TLI (TFT-LCD Interface) module handles the synchronous LCD interface and provides pixel data, clock and timing signals for passive LCD display. It supports a wide variety of displays with fully programmable timing parameters. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display.
Page 596: Figure 23-1. Tli Module Block Diagram
GD32F20x User Manual Figure 23-1. TLI module block diagram Interrupts RED[7:0] Registers Timing GREEN[7:0] BLUE[7:0] Controller Dithering Register PIXCLK Reloading Pixel Process Window Unit 0 Pixel & Pixel Process Blending Unit 1 23.4. Signal description TLI provides a 24-bit RGB parallel display interface, which is shown in table below. Table 23-1.
Page 597: Pixel Dma Function
GD32F20x User Manual VTSZ VASZ VBPSZ VPSZ HTSZ HASZ HBPSZ HPSZ PIXCLK RED[7:0], GREEN[7:0], BLUE[7:0] 23.5.2. Pixel DMA function Following the configuration of register module, the Pixel DMA reads pixel data from memory to the pixel buffer in internal PPU (Pixel Process Unit) continuously. After enabled, the Pixel DMA begins to fetch pixel data from system and push these data into the pixel buffer in PPU as long as the pixel buffer is not full.
Page 598: Table 23-2. Supported Pixel Formats
GD32F20x User Manual 23.5.3. Pixel formats The Pixel DMA pushes pixel data into PPU in word format and PPU (Pixel Process Unit) is responsible for converting various pixel formats into an internal ARGB8888 format. TLI supports up to eight pixel formats as shown in the table below. The PPF[2:0] in TLI_LxPPF register defines the pixel format.
Page 599: Figure 23-3. Block Diagram Of Blending
GD32F20x User Manual define a window inside the layer. The pixel inside the window will keep its original value, while the pixel outside will be replaced with a default pixel defined in TLI_LxDC register. The blending units first blends Layer0 and BG Layer into a temporary layer, and then blends Layer1 and the temporary layer into destination layer.
Page 600: Table 23-3. Status Flags
GD32F20x User Manual blanking and load the shadow registers. In both modes, hardware automatically clears the RQR or FBR bit after successfully reload. 23.5.6. Dithering function The dithering module adds a 2-bit pseudo-random value to each pixel channel. This function is able to make the image smoother when 18-bits interface is used to display a 24-bit data.
Page 601: Register Definition
GD32F20x User Manual 23.6. Register definition TLI start address: 0x4001 6800 23.6.1. Synchronous pulse size register (TLI_SPSZ) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved HPSZ[11:0] Reserved VPSZ[11:0] Bits Fields Descriptions 31:28 Reserved Must keep the reset value...
Page 602: Active Size Register (Tli_Asz)
GD32F20x User Manual Bits Fields Descriptions 31:28 Reserved Must keep the reset value 27:16 HBPSZ[11:0] Size of the horizontal back porch plus synchronous pulse The HBPSZ value should be configured to the pixels number of horizontal back porch and synchronous pulse minus 1. 15:12 Reserved Must keep the reset value...
Page 603: Control Register (Tli_Ctl)
GD32F20x User Manual Reserved HTSZ[11:0] Reserved VTSZ[11:0] Bits Fields Descriptions 31:28 Reserved Must keep the reset value 27:16 HTSZ[11:0] Horizontal total size of the display, including active area, back porch, synchronous pulse and front porch The HTSZ value should be configured to the pixels number of horizontal active area width plus back porch, front porch and synchronous pulse minus 1.
Page 604: Reload Layer Register (Tli_Rl)
GD32F20x User Manual 0: Data Enable active low 1: Data Enable active high CLKPS Pixel Clock Polarity Selection 0: Pixel Clock is TLI clock 1: Pixel Clock is inverted TLI clock 27:17 Reserved Must keep the reset value DFEN Dither Function Enable 0: Dither function disable 1: Dither function enable Reserved...
Page 605: Background Color Register (Tli_Bgc)
GD32F20x User Manual 31:2 Reserved Must keep the reset value Frame Blank Reload This bit is set by software and cleared by hardware after reloading 0: Reload disable 1: The layer configuration will be reloaded into core at frame blank Request Reload This bit is set by software and cleared by hardware after reloading 0: Reload disable...
Page 606: Interrupt Flag Register (Tli_Intf)
GD32F20x User Manual Bits Fields Descriptions 31:4 Reserved Must keep the reset value LCRIE Layer Configuration Reloaded Interrupt Enable 0: Layer configuration reloaded flag won’t generate an interrupt 1: Layer configuration reloaded flag will generate an interrupt TEIE Transaction Error Interrupt Enable 0: Transaction error flag won’t generate an interrupt 1: Transaction error flag will generate an interrupt FEIE...
Page 607: Interrupt Flag Clear Register (Tli_Intc)
GD32F20x User Manual 1: A FIFO under-run error occurs The under-run error occurs when the value written in TLI_LxFLLEN and TLI_LxFTLN is less than required. Line Mark Flag 0: No line mark flag 1: Line number reaches the specified value in TLI_LM 23.6.10.
Page 608: Current Pixel Position Register (Tli_Cppos)
GD32F20x User Manual Reserved Reserved LM[10:0] Bits Fields Descriptions 31:11 Reserved Must keep the reset value 10:0 LM[10:0] Line Mark value The LMF bit in TLI_INTF will be set after the line number reaches this value 23.6.12. Current pixel position register (TLI_CPPOS) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 609: Layer X Control Register (Tli_Lxctl)
GD32F20x User Manual Bits Fields Descriptions 31:4 Reserved Must keep the reset value Current HS status of the TLI Current VS status of the TLI Current HDE status 0: HPOS in TLI_CPPOS register is not between the HBPSZ in TLI_BPSZ register and HASZ in TLI_ASZ register.
Page 610: Layer X Horizontal Position Parameters Register (Tli_Lxhpos)
GD32F20x User Manual Bits Fields Descriptions 31:5 Reserved Must keep the reset value LUTEN LUT Enable 0: LUT is disabled 1: LUT is enabled Reserved Must keep the reset value CKEYEN Color Keying Enable 0: Color keying is disabled 1: Color keying is enabled Layer Enable 0: This layer is disabled 1: This layer is enabled...
Page 611: Layer X Color Key Register (Tli_Lxckey)
GD32F20x User Manual Reserved WBP[11:0] Reserved WTP[11:0] Bits Fields Descriptions 31:27 Reserved Must keep the reset value 26:16 WBP[11:0] Window Bottom Position 15:12 Reserved Must keep the reset value 11:0 WTP[11:0] Window Top Position 23.6.17. Layer x color key register (TLI_LxCKEY) Address offset: 0x90+0x80*x x=0 or 1 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 612: Layer X Specified Alpha Register (Tli_Lxsa)
GD32F20x User Manual Reserved Reserved PPF[2:0] Bits Fields Descriptions 31:3 Reserved Must keep the reset value PPF[2:0] Packeted Pixel Format These bits configures the Packeted Pixel format 000: ARGB8888 001: RGB888 010: RGB565 011: ARGB1555 100: ARGB4444 101: L8 110: AL44 111: AL88 23.6.19.
Page 613: Layer X Blending Register (Tli_Lxblend)
GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) DCA[7:0] DCR[7:0] DCG[7:0] DCB[7:0] Bits Fields Descriptions 31:24 DCA[7:0] The Default Color ALPHA 23:16 DCR[7:0] The Default Color Red 15:8 DCG[7:0] The Default Color Green DCB[7:0] The Default Color Blue The default color of a layer takes effect when the layer is disabled or outside the window...
Page 614: Layer X Frame Base Address Register (Tli_Lxfbaddr)
GD32F20x User Manual 111: Reserved Reserved Must keep the reset value ACF2[2:0] Alpha Calculation Factor 2 of Blending Method 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100: Reserved 101: 1-normalization Specified Alpha 110: Reserved 111: 1-normalization Pixel Alpha x normalization Specified Alpha 23.6.22.
Page 615: Layer X Frame Total Line Number Register (Tli_Lxftln)
GD32F20x User Manual Bits Fields Descriptions 31:30 Reserved Must keep the reset value 29:16 STDOFF[13:0] Frame Buffer Stride Offset This value defines the bytes number from start of a line to the start of next line 15:14 Reserved Must keep the reset value 13:0 FLL[13:0] Frame Line Length...
Page 616 GD32F20x User Manual 31:24 TADD[7:0] Look Up Table Write Address The entry at this address in LUT will be updated with the value of RED, GREEN and BLUE written 23:16 TR [7:0] Red Channel of a LUT entry 15:8 TG[7:0] Green Channel of a LUT entry TB [7:0] Blue Channel of a LUT entry...
Page 617: Secure Digital Input/Output Interface (Sdio)
GD32F20x User Manual Secure digital input/output interface (SDIO) 24.1. Overview The secure digital input/output interface (SDIO) defines the SD, SD I/O, MMC and CE-ATA card host interface, which provides command/data transfer between the AHB system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC) and CE-ATA devices. The supported SD memory card and SD I/O card system specifications are defined in the SD card Association website at www.sdcard.org.
Page 618: Figure 24-1 Sdio "No Response" And "No Data" Operations
GD32F20x User Manual Response: a response is a token which is sent from the card to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.
Page 619: Figure 24-2. Sdio Multiple Blocks Read Operation
GD32F20x User Manual Figure 24-2. SDIO multiple blocks read operation Figure 24-3. SDIO multiple blocks write operation SDIO_CMD Command Response Command Response Host to Device Device to Host Host to Device Device to Host SDIO_DAT DATA BLOCK CRC DATA BLOCK CRC Host to Device Host to Device Block write operation...
Page 620: Figure 24-6. Sdio Block Diagram
GD32F20x User Manual 24.4. SDIO function overview The following figure shows the SDIO structure. There have two main parts:  The SDIO adapter block consists of control unit which manage clock, command unit which manage command transfer, data unit which manage data transfer. ...
Page 621: Table 24-1. Sdio I/O Definitions
GD32F20x User Manual SDIO_DAT[7:0]: These are bidirectional data channels. The DAT signals operate in push-pull mode. Only the card or the host is driving these signals at a time. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7 (just for MMC4.2), by the SDIO controller.
Page 622 GD32F20x User Manual 0b00/0b10. There are short response which have 48 bits or long response which have 136 bits. The response stores in SDIO_RESP0 - SDIO_RESP3 registers. The command unit also generates the command status flags defined in SDIO_STAT register. Command state machine CS_Idle After reset, ready to send command.
Page 623 GD32F20x User Manual → 1.CE-ATA Command Completion signal received CS_Idle → 2.CSM disabled CS_Idle → 3.Command CRC failed CS_Idle Data unit The data unit performs data transfers to and from cards. The data transfer uses SDIO_DAT[7:0] signals when 8-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b10), use SDIO_DAT[3:0] signals when 4-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b01), or SDIO_DAT[0] signal when 1-bit data width (BUSMODE bits in SDIO_CLKCTL register is 0b00).
Page 624: Ahb Interface
GD32F20x User Manual Note: The data timeout programmed in the data timer register (SDIO_DATATO). DS_WaitR Wait for the start bit of the receive data. → 1.Data receive ended DS_Idle → 2.DSM disabled DS_Idle → 3.Data timeout reached DS_Idle → 4.Receives a start bit before timeout DS_Receive Note: The data timeout programmed in the data timer register (SDIO_DATATO).
Page 625: Card Function Overview
GD32F20x User Manual 5. Write block to card as follows: Write the data size in bytes in the SDIO_DATALEN register. Write the block size in bytes (BLKSZ) in the SDIO_DATACTL register; the host sends data in blocks of size BLKSZ each. Program SDIO_CMDAGMT register with the data address, where data should be written.
Page 626 GD32F20x User Manual of the card and the access mode indication (MMC). In addition, this register includes a status information bit. This status bit is set if the card power up procedure has been finished. The register is a little different between MMC and SD card. The host can use CMD1 (MMC), ACMD41 (SD memory), CMD5 (SD I/O) to get the content of this register.
Page 627: Figure 24-7. Command Token Format
GD32F20x User Manual 24.5.2. Commands Commands types There are four kinds of commands defined to control the Card:  Broadcast commands (bc), no response  Broadcast commands with response (bcr), response from all cards simultaneously  Addressed (point-to-point) commands (ac), no data transfer on DAT ...
Page 628: Table 24-3. Card Command Classes (Cccs)
GD32F20x User Manual of each card, providing the host with information on how to access the card. For MMC cards, Class 0 is mandatory and shall be supported. The other classes are either mandatory only for specific card types or optional. By using different classes, several configurations can be chosen (e.g.
Page 629 GD32F20x User Manual Card command class(CCC) Supported Class command description CMD17 CMD18 CMD19 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61 ACMD6 ACMD13 ACMD22...
Page 630: Table 24-4. Basic Commands (Class 0)
GD32F20x User Manual Card command class(CCC) Supported Class command description ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC. CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card. CMD60, CMD61 are only available for CE-ATA device. 2.
Page 631 GD32F20x User Manual Response type argument Abbreviation Description index format Only for I/O cards. It is similar to [31:25]reserved the operation of ACMD41 for SD bits IO_SEND_OP_CO CMD5 memory cards, used to inquire [24]S18R about the voltage range needed [23:0] I/O OCR by the I/O card.
Page 632: Table 24-5. Block-Oriented Read Commands (Class 2)
GD32F20x User Manual Response type argument Abbreviation Description index format Sends an addressed card into [31:16] RCA the Inactive State. This GO_INACTIVE_ CMD15 [15:0] reserved command is used when the host STATE bits explicitly wants to deactivate a card. A host sends the bus test data CMD19 adtc [31:0] stuff bits...
Page 633: Table 24-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32F20x User Manual Response type argument Abbreviation Description index format address _BLOCK blocks from card to host until interrupted by a STOP_TRANSMISSION command. Block length is specified the same as READ_SINGLE_BLOCK command. Note: The transferred data must not cross a physical block boundary, unless READ_BLK_MISALIGN is set in the CSD register Table 24-6.
Page 634: Table 24-8. Erase Commands (Class 5)
GD32F20x User Manual Response type argument Abbreviation Description index format In the case of a Standard Capacity SD, this command writes a block of the size selected by the [31:0] data CMD24 adtc WRITE_BLOCK SET_BLOCKLEN command. In address the case of a SDHC, block length is fixed 512 Bytes regardless of the SET_BLOCKLEN command.
Page 635: Table 24-9. Block Oriented Write Protection Commands (Class 6)
GD32F20x User Manual Response type argument Abbreviation Description index format address START erase group within a range to be selected for erase.(MMC) Sets the address of the last [31:0]data ERASE_GROUP_ erase CMD36 address group within a continuous range to be selected for erase.(MMC) Erases all previously selected CMD38 [31:0] stuff bits...
Page 636: Table 24-11. Application-Specific Commands (Class 8)
GD32F20x User Manual index format See description in Table 24-5. [31:0] block CMD16 SET_BLOCK_LEN Block-Oriented read length commands (class Used to set/reset the password or lock/unlock the card. The size [31:0] of the data block is set by the CMD42 adtc Reserved bits LOCK_UNLOCK...
Page 637: Table 24-12. I/O Mode Commands (Class 9)
GD32F20x User Manual Response type argument Abbreviation Description index format for writing data to the card. [31] WR [23:18] Address R1(read)/ RW_MULTIPLE_ Read or write register in CMD60 adtc [7:2] Byte Count R1b(write) REGISTER address range. Other bits are reserved bits. [31] WR [15:0] Data Unit R1(read)/...
Page 638: Table 24-13. Switch Function Commands (Class 10)
GD32F20x User Manual Response type argument Abbreviation Description index format Data/Stuff Bits common use is to initialize registers or monitor status values for I/O functions. This command is the fastest means to read or write single I/O registers, as it requires only a single command/response pair.
Page 639: Figure 24-8. Response Token Format
GD32F20x User Manual 24.5.3. Responses All responses are sent on the CMD line. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type. Responses types There are 7 types of responses show as follows.
Page 640: Table 24-14. Response R1
GD32F20x User Manual R1 (normal response command) Code length is 48 bits. The bits 45:40 indicate the index of the command to be responded to, this value being interpreted as a binary coded number (between 0 and 63). The status of the card is coded in 32 bits.
Page 641: Table 24-17. Response R4 For Mmc
GD32F20x User Manual register R4 (Fast I/O) For MMC only. Code length is 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its contents. The status bit in the argument is set if the operation was successful.
Page 642: Table 24-20. Response R5 For Sd I/O
GD32F20x User Manual For SD I/O only. The SDIO card's response to CMD52 and CMD53 is R5. If the communication between the card and host is in the 1-bit or 4-bit SD mode, the response shall be in a 48-bit response (R5).
Page 643: Figure 24-9. 1-Bit Data Bus Width
GD32F20x User Manual 1-bit data packet format After card reset and initialize, only DAT0 pin is used to transfer data. And other pin can be used freely. Figure 24-9. 1-bit data bus width, Figure 24-10. 4-bit data bus width Figure 24-11. 8-bit data bus width show the data packet format when data bus wide is 1-bit, 4-bit and 8-bit.
Page 644: Table 24-23. Card Status
GD32F20x User Manual 24.5.5. Two status fields of the card The SD Memory supports two status fields and others just support the first one: Card Status: Error and state information of a executed command, indicated in the response SD Status: Extended status field of 512 bits that supports special features of the SD Memory Card and future Application-Specific features.
Page 645 GD32F20x User Manual Bits Identifier Type Value Description Clear Condition ’1’= error is not allowed for this card, or the number of transferred bytes does not match the block length. ’0’= no error ERASE_SEQ_ERROR An error in the sequence of ’1’= error erase commands occurred.
Page 646 GD32F20x User Manual Bits Identifier Type Value Description Clear Condition CSD does not match the card content. - An attempt to reverse the copy (set as original) or permanent WP(unprotected) bits was made. ’0’= not protected WP_ERASE_SKIP Set when only partial address ’1’= protected space was erased due to existing write protected...
Page 647: Table 24-24. Sd Status
GD32F20x User Manual Bits Identifier Type Value Description Clear Condition interpreted as ACMD. Reserved ’0’= no error AKE_SEQ_ERROR Only for SD memory. Error in ’1’= error the sequence of the authentication process. Reserved for application specific commands. [1:0] Reserved for manufacturer test mode. Note: 18, 17, 7 bits are only for MMC.
Page 648 GD32F20x User Manual Bits Identifier Type Value Description Clear Condition ED_AREA area [447:4 SPEED_CLASS Speed class of the (See below) card [439:4 PERFORMANCE_M Performance of (See below) move indicated by 1 [MB/s] step. [431:4 AU_SIZE Size of AU (See below) [427:4 reserved [423:4...
Page 649: Table 24-25. Performance Move Field
GD32F20x User Manual 02h: Class 4 03h: Class 6 04h: Class 10 05h–FFh: Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm and the value can be set by 1 [MB/sec] step. If the card does not move useing RUs, Pm should be considered as infinity. Setting to FFh means infinity. The minimum value of Pm is defined in Table 24-25.
Page 650: Table 24-28. Erase Size Field
GD32F20x User Manual than or equal to the maximum AU size. The card should set smaller AU size as possible. Table 24-27. Maximum AU size Card Capacity up to 64MB up to 256MB up to 512MB up to 32GB up to 2TB Maximum AU 512 KB 1 MB...
Page 651: Table 24-30. Erase Offset Field
GD32F20x User Manual This 2-bit field indicates the T and one of four values can be selected. This field is OFFSET meaningless if ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 24-30. Erase offset field ERASE_OFFSET Value Definition 0 [sec] 1 [sec] 2 [sec] 3 [sec]...
Page 652 GD32F20x User Manual this command. If the card cannot perform data transfer in the specified range it must discard itself from further bus operations and go into Inactive State. Otherwise, the card shall respond sending back its V range. If the card can operate on the supplied voltage, the response echoes back the supply voltage and the check pattern that were set in the command argument.
Page 653: No Data Commands
GD32F20x User Manual – presence CE-ATA device, FAST_IO (CMD39) RW_MULTIPLE_REGISTER (CMD60) commands will succeed and the returned data will be the CE-ATA reset signature. 24.6.2. No data commands To send any non-data command, the software needs to program the SDIO_CMDCTL register and the SDIO_CMDAGMT register with appropriate parameters.
Page 654: Single Block Or Multiple Block Read
GD32F20x User Manual to low if programming is still in progress and the write buffer is unavailable. For SD card. Setting a number of write blocks to be pre-erased (ACMD23) will make a following Multiple Block Write operation faster compared to the same operation without preceding ACMD23.
Page 655: Stream Write And Stream Read (Mmc Only)
GD32F20x User Manual The data transfer stops after the end bit of the stop command. When the last block of user area is read using CMD18, the host should ignore OUT_OF_RANGE error that may occur even the sequence is correct. If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed, the card shall detect a block misalignment at the beginning of the first misaligned block, set the ADDRESS_ERROR error bit in the status register, abort...
Page 656 GD32F20x User Manual Note that the stream write command works only on a 1 bit bus configuration (on DAT0). If CMD20 is issued in other bus configurations, it is regarded as an illegal command. In order to sustain data transfer in stream mode of the card, the time it takes to receive the data (defined by the bus clock rate) must be less than the time it takes to program it into the main memory field (defined by the card in the CSD register).
Page 657: Erase
GD32F20x User Manual READ_BL_LEN -100*NSAC max read frequence = min (TRAN_SPEED, (24-3) TAAC*R2W_FACTOR TRAN_SPEED: Max bus clock frequency. READ_BL_LEN: Max read data block length. NSAC: Data read access-time 2 in CLK cycles. TAAC: Data read access-time 1. R2W_FACTOR: Write speed factor. All the parameters are defined in CSD register.
Page 658: Bus Width Selection
GD32F20x User Manual holding DAT0 low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card. 24.6.7. Bus width selection After the host has verified the functional pins on the bus it should change the bus width configuration.
Page 659: Table 24-31. Lock Card Data Structure
GD32F20x User Manual 24.6.9. Card Lock/Unlock operation The password protection feature enables the host to lock a card while providing a password, which later will be used for unlocking the card. The password and its size are kept in a 128- bit PWD and 8-bit PWD_LEN registers, respectively.
Page 660 GD32F20x User Manual  Select a card (CMD7), if not previously selected.  Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the new password. In the case that a password replacement is done, then the block size shall consider that both passwords (the old and the new one) are sent with the command.
Page 661: Specific Operations
GD32F20x User Manual  Select a card (CMD7), if not previously selected.  Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the currently used password. ...
Page 662: Figure 24-12. Read Wait Control By Stopping Sdio_Clk
GD32F20x User Manual Figure 24-12. Read wait control by stopping SDIO_CLK Figure 24-13. Read wait operation using SDIO_DAT[2] 2 CLK 2 CLK 2 CLK 4 CLK min(no wait) We can start the Read Wait interval before the data block is received: when the data unit is enabled (SDIO_DATACTL[0] bit set), the SD I/O specific operation is enabled (SDIO_DATACTL[11] bit set), Read Wait starts (SDIO_DATACTL[10] = 0 and SDIO_DATACTL[8] = 1) and data direction is from card to SD I/O (SDIO_DATACTL[1] = 1),...
Page 663: Figure 24-15. Read Interrupt Cycle Timing
GD32F20x User Manual completed, the resume is issued to function, causing the data transfer to resume (DF=1). Figure 24-14. Function2 read cycle inserted during function1 multiple read cycle When the host sends data to the card, the host can suspend the write operation. The SDIO_CMDCTL[11] bit is set and indicates to the CSM that the current command is a suspend command.
Page 664: Figure 24-16. Write Interrupt Cycle Timing
GD32F20x User Manual Figure 24-16. Write interrupt cycle timing When transferring multiple blocks of data in the 4-bit SD mode, a special definition of the interrupt period is required. In order to allow the highest speed of communication, the interrupt period is limited to a 2-clock interrupt period.
Page 665: Figure 24-19. The Operation For Command Completion Disable Signal
GD32F20x User Manual normal ATA command completion or when ATA command termination has occurred due to an error condition the device has encountered. If the ‘enable CMD completion’ bit SDIO_CMDCTL[12] is set and the ‘not interrupt Enable’ bit SDIO_CMDCTL[13] is reset, the CSM waits for the command completion signal in the Waitcompl state.
Page 666: Register Definition
GD32F20x User Manual 24.8. Register definition SDIO start address: 0x4001 8000 24.8.1. Power control register (SDIO_PWRCTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value PWRCTL[1:0] SDIO power control bits.
Page 667 GD32F20x User Manual Bits Fields Descriptions DIV[8] MSB of Clock division This field defines the MSB division between the input clock (SDIOCLK) and the output clock, refer to bit 7:0 of SDIO_CLKCTL 30:15 Reserved Must be kept at reset value HWCLKEN Hardware Clock Control enable bit If this bit is set, hardware controls the SDIO_CLK on/off depending on the system...
Page 668: Command Argument Register (Sdio_Cmdagmt)
GD32F20x User Manual 24.8.3. Command argument register (SDIO_CMDAGMT) Address offset: 0x08 Reset value: 0x0000 0000 This register defines 32 bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit) CMDAGMT[31:16] CMDAGMT[15:0] Bits...
Page 669 GD32F20x User Manual NINTEN No CE-ATA Interrupt (CE-ATA only) This bit defines if there is CE-ATA interrupt or not. This bit is only used when CE- ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card.
Page 670: Table 24-32. Sdio_Respx Register At Different Response Type
GD32F20x User Manual 24.8.5. Command index response register (SDIO_RSPCMDIDX) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RSPCMDIDX[5:0] Last response command index Read-only bits field.
Page 671: Data Timeout Register (Sdio_Datato)
GD32F20x User Manual Register Short response Long response SDIO_RESP1 reserved Card response [95:64] SDIO_RESP2 reserved Card response [63:32] SDIO_RESP3 reserved Card response [31:1],plus bit 0 24.8.7. Data timeout register (SDIO_DATATO) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DATATO[31:16] DATATO[15:0] Bits...
Page 672: Data Control Register (Sdio_Datactl)
GD32F20x User Manual Bits Fields Descriptions 31:25 Reserved Must be kept at reset value 24:0 DATALEN[24:0] Data transfer length This register defined the number of bytes to be transferred. When the data transfer starts, the data counter loads this register and starts decrement. Note: If block data transfer selected, the content of this register must be a multiple of the block size (refer to SDIO_DATACTL).
Page 673 GD32F20x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value IOEN SD I/O specific function enable(SD I/O only) 0: Not SD I/O specific function 1: SD I/O specific function RWTYPE Read wait type(SD I/O only) 0: Read Wait control using SDIO_DAT[2] 1: Read Wait control by stopping SDIO_CLK RWSTOP Read wait stop(SD I/O only)
Page 674: Status Register (Sdio_Stat)
GD32F20x User Manual 1: Read data from card. DATAEN Data transfer enable bit Write 1 to this bit to start data transfer regardless this bit is 0 or 1. The DSM moves to Readwait state if RWEN is set or to the WaitS, WaitR state depend on DATADIR bit.
Page 675: Interrupt Clear Register (Sdio_Intc)
GD32F20x User Manual Receive FIFO is full When HW Flow control is enabled, RFF signals becomes activated 2 words before the FIFO is full. Transmit FIFO is full Receive FIFO is half full: at least 8 words can be read in the FIFO Transmit FIFO is half empty: at least 8 words can be written into the FIFO RXRUN Data reception in progress...
Page 676: Interrupt Enable Register (Sdio_Inten)
GD32F20x User Manual DTBLK DTTMOU DTCRC CCRC Reserved STBITEC DTENDC RXOREC TXUREC ENDC SENDC RECVC TMOUTC ERRC ERRC Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDC ATAEND flag clear bit Write 1 to this bit to clear the flag. SDIOINTC SDIOINT flag clear bit Write 1 to this bit to clear the flag.
Page 677 GD32F20x User Manual This register enables the corresponding interrupt in the SDIO_STAT register. This register has to be accessed by word(32-bit) ATAENDI SDIOINTI RXDT TXDTVAL Reserved RFEIE TFEIE RFFIE TFFIE VALIE CMDRUN DTBLK DTCRC CCRC RFHIE TFHIE RXRUNIE TXRUNIE STBITEIE DTENDIE RXOREIE TXUREIE ENDIE SENDIE...
Page 678: Fifo Counter Register (Sdio_Fifocnt)
GD32F20x User Manual Write 1 to this bit to enable the interrupt. DTBLKENDIE Data block end interrupt enable Write 1 to this bit to enable the interrupt. STBITEIE Start bit error interrupt enable Write 1 to this bit to enable the interrupt. DTENDIE Data end interrupt enable Write 1 to this bit to enable the interrupt.
Page 679: Fifo Data Register (Sdio_Fifo)
GD32F20x User Manual 31:24 Reserved Must be kept at reset value 23:0 FIFOCNT[23:0] FIFO counter. These bits define the remaining number words to be written or read from the FIFO. It loads the data length register (SDIO_DATALEN[24:2] if SDIO_DATALEN is word- aligned or SDIO_DATALEN[24:2]+1 if SDIO_DATALEN is not word-aligned) when DATAEN is set, and start count decrement when a word write to or read from the FIFO.
Page 680: External Memory Controller (Exmc)
GD32F20x User Manual External memory controller (EXMC) 25.1. Overview The external memory controller EXMC, is used as a translator for CPU to access a variety of external memory, it automatically converts AMBA memory access protocol into a specific memory access protocol defined in the configuration register, such as SRAM, ROM, NOR Flash, PSRAM, NAND Flash, PC Card and SDRAM.
Page 681: Figure 25-1. The Exmc Block Diagram
GD32F20x User Manual 25.3. Function overview 25.3.1. Block diagram EXMC is the combination of six modules: The AHB bus interface, EXMC configuration registers, NOR/PSRAM controller, NAND/PC Card controller, SDRAM controller and external device interface. AHB clock (HCLK) is the reference clock. Figure 25-1.
Page 682: Figure 25-2. Exmc Memory Banks
GD32F20x User Manual automatically split into several continuous memory accesses. When the width of AHB bus is smaller than memory bus width. If the external memory devices have the byte selection function, such as SRAM, ROM. PSRAM, SDRAM, the application can access the corresponding byte through their byte lane EXMC_NBL[1:0].
Page 683: Figure 25-3. Four Regions Of Bank0 Address Mapping
GD32F20x User Manual Bank1 and Bank2 are used to access NAND Flash exclusively. Bank3 is used for PCCard access. SDRAM Device0 and Device1 are used for Synchronous DRAM (SDRAM) access. NOR/PSRAM address mapping Figure 25-3. Four regions of bank0 address mapping reflects the address mapping of the four regions of bank0.
Page 684: Figure 25-4. Nand/Pc Card Address Mapping
GD32F20x User Manual NAND/PC card address mapping Bank1 and bank2 are designed to access NAND Flash, and bank3 is designed to access PC Card. Each bank is further divided into several memory spaces as shown in Figure 25-4. NAND/PC card address mapping.
Page 685: Figure 25-5. Diagram Of Bank1 Common Space
GD32F20x User Manual Figure 25-5. Diagram of bank1 common space EXMC Memory Address Memory Space HADDR[17:16] Bank 0x70000000 Data Area 0x7000 FFFF 0x70010000 Command Area 0x7001 FFFF Bank1 0x70020000 Common Address Area 0x7003 Space FFFF 0x70040000 0x73FF FFFF HADDR [17:16] bits are used to select one of the three areas. ...
Page 686: Figure 25-6. Sdram Address Mapping
GD32F20x User Manual Figure 25-6. SDRAM address mapping HADDR[28] Address Banks Supported memory type 0xC000 0000 SDRAM Bank0 SDRAM 0xCFFF FFFF 0xD000 0000 SDRAM Bank1 SDRAM 0xDFFF FFFF The following table shows SDRAM address mapping of a 13-bit row and an 11-bit column configuration.
Page 687: Table 25-3. Psram Non-Muxed Signal Description
GD32F20x User Manual EXMC Pin Direction Mode Functional description EXMC_A[25:0] Muxed EXMC_A[25:16] Async/Sync Input/output Address/Data bus (muxed) EXMC_D[15:0] Async/Sync Input/output Data bus (non-muxed) Chip selection, EXMC_NE[x] Output Async/Sync x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE Output Async/Sync Write enable EXMC_NWAIT Input Async/Sync Wait input signal...
Page 688: Table 25-5. Exmc Bank 0 Supports All Transactions
GD32F20x User Manual Table 25-5. EXMC bank 0 supports all transactions Memory Memory Access Mode Transaction Transaction Comments Size Size Async Async Async Split into 2 EXMC Async NOR Flash accesses Split into 2 EXMC Async accesses Sync Sync Async Use of byte lanes Async EXMC_NBL[1:0]...
Page 689: Table 25-6. Nor / Psram Controller Timing Parameters
GD32F20x User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size Async Async NOR Flash/PSRAM controller timing EXMC provides various programmable timing parameters and timing models for SRAM, ROM, PSRAM, NOR Flash and other external static memory. Table 25-6. NOR / PSRAM controller timing parameters Parameter Function Access mode...
Page 690: Figure 25-7. Mode 1 Read Access
GD32F20x User Manual Timing Extend Write timing Read timing Mode description model mode parameter parameter DLAT DLAT Mode SM NOR Flash address/data mux CKDIV CKDIV As shown in Table 25-7. EXMC_timing models, EXMC NOR Flash / PSRAM controller provides a variety of timing model, users can modify those parameters listed in Table 25-6.
Page 691 GD32F20x User Manual Bit Position Bit Name Reference Setting Value 31-20 Reserved 0x000 SYNCWR 18-16 Reserved ASYNCWAIT Depends on memory EXMODEN NRWTEN Depends on user NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN...
Page 692: Figure 25-9. Mode A Read Access
GD32F20x User Manual Figure 25-9. Mode A read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time (ASET HCLK) (DSET HCLK) Figure 25-10. Mode A write access Address (EXMC_A[25:0]) Chip Enable...
Page 693: Figure 25-11. Mode 2/B Read Access
GD32F20x User Manual SBRSTEN Reserved NREN No effect Depends on memory NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx(Read) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+1 HCLK for...
Page 694: Figure 25-12. Mode 2 Write Access
GD32F20x User Manual Figure 25-12. Mode 2 write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET HCLK) (DSET HCLK) Figure 25-13. Mode B write access Address (EXMC_A[25:0]) Chip Enable...
Page 695: Figure 25-14. Mode C Read Access
GD32F20x User Manual NRTP 0x2，NOR Flash NRMUX NRBKEN EXMC_SNTCFGx(Read and write in mode 2,read in mode B) 31-30 Reserved 0x0000 29-28 ASYNCMOD Mode B:0x1 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge 15-8 DSET...
Page 696: Figure 25-15. Mode C Write Access
GD32F20x User Manual Figure 25-15. Mode C write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET HCLK) (WDSET HCLK) The different between mode C and mode 1 write timing is that read/write timing is specified by the same set of timing configuration, while mode C write timing configuration is independent of its read configuration.
Page 697: Figure 25-16. Mode D Read Access
GD32F20x User Manual EXMC_NE[x] falling edge 15-8 DSET Depends on memory and user AHLD ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode C:0x2 27-24 DLAT 23-20 CKDIV 19-16 Reserved 15-8 WDSET Depends on memory and user WAHLD WASET Depends on memory and user...
Page 698 GD32F20x User Manual Bit Position Bit Name Reference Setting Value 31-20 Reserved 0x000 SYNCWR 18-16 Reserved ASYNCWTEN Depends on memory EXMODEN NRWTEN Depends on user NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN...
Page 699: Figure 25-18. Multiplex Mode Read Access
GD32F20x User Manual Figure 25-18. Multiplex mode read access Address Address[25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Mux Address[15:0] Memory Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time (ASET HCLK) (AHLD HCLK) (DSET HCLK) Figure 25-19.
Page 700 GD32F20x User Manual NRTP 0x2:NOR Flash NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT No effect 23-20 CKDIV No effect Minimum time between EXMC_NE[x] rising edge 19-16 BUSLAT to EXMC_NE[x] falling edge 15-8 DSET Depends on memory and user AHLD Depends on memory and user ASET...
Page 701: Figure 25-20. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32F20x User Manual Figure 25-20. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1 Output Enable (EXMC_NOE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 4 HCLK Figure 25-21.
Page 702 GD32F20x User Manual NOR Flash latency = DLAT + 3 Data wait Users should guarantee that EXMC_NWAIT signal’s behavior matches that of the external device. This signal’s feature is configured through the EXMC_SNCTLx registers, it is enabled by the NRWTEN bit, and the active timing could be one data cycle before the wait state or active during the active state by the configuration NRWTCFG bit, while the wait signal’s polarity is set by the NRWTPOL bit.
Page 703: Figure 25-22. Synchronous Mux Burst Read Timing
GD32F20x User Manual Figure 25-22. Synchronous mux burst read timing HCLK Clock (EXMC_CLK) Address Address [25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Wait (EXMC_NWAIT) Data Memory Memory Memory Address [15:0] (EXMC_D[15:0]) Data 1 Data 2 Data 3 Data Latency (DATLAT + 2 HCLK)
Page 704: Figure 25-23. Synchronous Mux Burst Write Timing
GD32F20x User Manual Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge 15-8 DSET No effect AHLD No effect ASET No effect Mode SM –Synchronous mux burst write timing – PSRAM (CRAM) Figure 25-23. Synchronous mux burst write timing HCLK Clock (EXMC_CLK)
Page 705: Table 25-16. Spi/Qpi Interface
GD32F20x User Manual NRTP NRMUX 0x1, Depends on users NRBKEN EXMC_SNTCFGx(Write) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1,EXMC_CLK=2HCLK Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge 15-8 DSET No effect AHLD No effect ASET...
Page 706: Figure 25-24. Spi-Psram Access
GD32F20x User Manual data to be received is read from the same region. Read device ID Read device ID command is a special command, it is issued by first polling the SC bit until it is 0, then set SC to 1. Lower 32-bit ID read is stored in EXMC_SIDL register, and the upper 32-bit ID read is stored in EXMC_SIDH register.
Page 707: Figure 25-25. Sqpi-Psram Access
GD32F20x User Manual Figure 25-25. SQPI-PSRAM access Clock (EXMC_CLK) Chip Enable (EXMC_NEx) Data (EXMC_D[0]) Command Data (EXMC_D[1]) Data (EXMC_D[2]) Data (EXMC_D[3]) Command, width Address, 24-bits Wait Data 1 Data 2 depends on CMDBIT QPI-PSRAM access timing The only difference between SQPI and QPI mode is that the command is sent parallel on the 4 data IO lines as shown in the diagram below.
Page 708: Table 25-17. 8-Bit Or 16-Bit Nand Interface Signal
GD32F20x User Manual NAND flash or PC card interface function Table 25-17. 8-bit or 16-bit NAND interface signal EXMC Pin Direction Functional description EXMC_A[17] Output NAND Flash address latch（ALE） EXMC_A[16] Output NAND Flash command latch（CLE） 8-bit multiplexed, bidirectional address/data bus EXMC_D[7:0]/ Input /Output EXMC_D[15:0]...
Page 709: Figure 25-27. Access Timing Of Common Memory Space Of Nand Flash Or Pc Card Controller
GD32F20x User Manual Memory Mode AHB transaction size Comments Async Async Automatically split into 2 EXMC accesses Async NAND flash or PC card controller timing EXMC can generate the appropriate signal timing for NAND Flash, PC Cards and other devices. Each bank has a corresponding register to manage and control the external memory, such as EXMC_NPCTLx, EXMC_NPINTENx, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 and EXMC_NECCx.
Page 710 GD32F20x User Manual controller Clock (EXMC_CLK) Address (EXMC_A[25:0]) Chip Enable (EXMC_NCE) EXMC_NREG EXMC_NIORD EXMC_NIOWR EXMC_NWR EXMC_NOE Write Data Read Data Valid COMSETx + 1 HCLK COMHLDx HCLK COMHIZx HCLK COMWAITx + 1 HCLK NAND flash operation When EXMC sends command or address to NAND Flash, it needs to use the command latch signal (A [16]) or address latch signal (EXMC_A [17]), namely, the CPU needs to perform write operation in particular address.
Page 711: Figure 25-28. Access To None "Nce Don't Care" Nand Flash
GD32F20x User Manual sensitive NAND Flash also requires that the EXMC_NCE must remain valid before it is ready. Taking TOSHIBA128 M x 8 bit NAND Flash as an example: Figure 25-28. Access to none "NCE don’t care" NAND Flash Chip Enable (EXMC_NCE) Command Latch Enable...
Page 712 GD32F20x User Manual needed, software must clear the EXMC_NECCx register value by resetting ECCEN bit of EXMC_NPCTLx register to zero, and then restart ECC calculation by setting the ECCEN bit of EXMC_NPCTLx to one. PC/CF card access EXMC Bank3 is used exclusively for PC/CF Card, both memory and IO mode access are supported.
Page 713: Sdram Controller
GD32F20x User Manual IO space: Both byte and half-word AHB access are supported, in IO space memory access, EXMC_NIORD and EXMC_NIOWR act as the read and write enable signal respectively. 25.3.6. SDRAM controller Characteristics  Two independent SDRAM devices  8-,16- or 32-bit data bus width ...
Page 714 GD32F20x User Manual SDRAM overview Synchronous dynamic random-access memory (SDRAM) is a dynamic random access memory (DRAM) whose external interface is coordinated by a synchronous external clock, this clock is provided by the EXMC through the SDRAM clock (EXMC_SDCLK) pin, and its frequency could be configured to be fHCLK/2 or fHCLK /3 according to the SDRAM clock configuration bit (SDCLK) in the EXMC_SDCTLx register.
Page 715: Figure 25-29. Sdram Controller Block Diagram
GD32F20x User Manual interface between MCU and SDRAM memory. It translates AHB transactions into the appropriate SDRAM protocol, and meanwhile, makes sure the access timing requirements of the external SDRAM devices are satisfied by the configuration of EXMC_SDTCFG register. SDRAMC could be divided into 4 sub-modules, the read/write split, control registers, finite state machine, and signal generator.
Page 716: Table 25-22. Io Definition Of Sdram Controller
GD32F20x User Manual A[n] A[10] A[m] Command Bank Burst write to current row Bank Burst write to current row, precharge when done Bank Active, open row for read/write Bank Precharge, close current row of the selected bank Precharge all, close current row of all banks Auto-refresh when SDCKE = 1 Self-refresh when SDCKE = 0 Mode...
Page 717 GD32F20x User Manual Timing parameter specification: SDRAM timing configuration register EXMC_SDTCFGx should be programed according to external SDRAM data sheet for SDRAM controller to keep pace with the operation of the external SDRAM. RPD and ARFD must be programed in EXMC_SDTCFG0, those corresponding bit position in EXMC_SDTCFG1 are reserved.
Page 718: Figure 25-30. Burst Read Operation
GD32F20x User Manual Activate The activate command activates an idle bank. It presents a 2-bit bank address EXMC_A[15:14] and a 13-bit row address EXMC_A[12:0], and causes a read of that row into the bank’s array of 16,384 column sense amplifiers. This also known as opening the row. This operation has the side effect of refreshing the dynamic memory storage cells of that row.
Page 719: Figure 25-31. Data Sampling Clock Delay Chain
GD32F20x User Manual sample read data from external memories. This clock can be helpful when the read data can’t be sampled correctly by HCLK. When this clock is enabled, the read data will be firstly stored in an asynchronous FIFO before returned to the AHB bus. Additional delays of about 2~3 HCLK may be brought into the reading command process.
Page 720: Figure 25-32. Burst Write Operation
GD32F20x User Manual Figure 25-32. Burst write operation Clock (EXMC_SDCLK) Address (EXMC_A[12:0]) m+10 Bank Address bank bank (EXMC_A[15:14]) Chip Enable (EXMC_SDNEx) Row Address Strobe (EXMC_NRAS) Column Address Strobe (EXMC_NCAS) Write Enable (EXMC_SDNWE) Data (EXMC_D[31:0]) m+10 RCD = 3 Write Active Row Command The RW split module accepts AHB commands, and transfers them to single read/write accesses on the SDRAM memory according to the ratio of the data width between the AHB...
Page 721: Figure 25-34. Read Access When Fifo Hit (Brstrd=1)
GD32F20x User Manual Figure 25-33. Read access when FIFO not hit (BRSTRD=1, CL=2, SDCLK=2, PIPED=2) AHB Master IF Read @0x0 Data0 @0x0 Data1 Data2 Data3 @0x4 @0x8 @0xC Read FIFO Data1 @0x4 SDRAM Data2 @0x8 Memroy Data3 @0xc Figure 25-34. Read access when FIFO hit (BRSTRD=1) AHB Master IF Data2 @0x8 Read @0x8...
Page 722: Figure 25-35. Cross Boundary Read Operation
GD32F20x User Manual precharge command is issued. The precharge command is used to deactivate an active row in a particular bank or the active row in all banks. A precharge command must be issued before activating a different row in the same bank. Active and precharge are automatically issued by the EXMC, its correctness depends on memory dimension configurations discussed previously, read and write timing diagram concerning automatic row activation and precharge are depicted as follows.
Page 723: Figure 25-37. Process For Self-Refresh Entry And Exit
GD32F20x User Manual Precharge delay (PRD) and row to column delay (RCD) are added according to their configuration in EXMC_SDTCFGx register, other timing parameters should be configured as SDRAM specification requires. When this boundary happens to be at the end of a bank, two cases are possible: When the current bank is not the last bank, the activation of the first row of the next bank is performed, and this supports all row, column, and bus width configuration.
Page 724: Figure 25-38. Process For Power-Down Entry And Exit
GD32F20x User Manual Figure 25-38. Process for power-down entry and exit Clock (EXMC_SDCLK) Clock Enable (EXMC_SDCKE]) Command Active Power-down Entry Power-down Exit Status and interrupt The not ready status NRDY bit in EXMC_SDSTAT register specifies whether the SDRAM controller is ready for a new command, this bit is cleared immediately after the command in the SDRAMC’s internal register is sent.
Page 725: Register Definition
GD32F20x User Manual 25.4. Register definition EXMC start address: 0x6000 0000 25.4.1. NOR/PSRAM controller registers The peripheral registers have to be accessed by words (32-bit). SRAM/NOR flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0000 30DA This register has to be accessed by word (32-bit) SYNC...
Page 726 GD32F20x User Manual WREN Write enable 0: Disabled write in the bank by the EXMC, otherwise an AHB error is reported 1: Enabled write in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only work in synchronous mode 0: NWAIT signal is active one data cycle before wait state 1: NWAIT signal is active during wait state WRAPEN...
Page 727 GD32F20x User Manual This register has to be accessed by word(32-bit) Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0] DSET[7:0] AHLD[3:0] ASET[3:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:28 ASYNCMOD[1:0] Asynchronous access mode The bits are valid only when the EXMEN bit in the EXMC_SNCTLx register is 1. 00: Mode A access 01: Mode B access 10: Mode C access...
Page 728 GD32F20x User Manual This field is used to set the time of address hold phase, which only used in mode D and multiplexed mode. 0x0: Reserved 0x1: Address hold time = 2 * HCLK …… 0xF: Address hold time = 16 * HCLK ASET[3:0] Address setup time This field is used to set the time of address setup phase.
Page 729: Nand Flash/Pc Card Controller Registers
GD32F20x User Manual 23:20 CKDIV[3:0] Synchronous clock divide ratio. This filed is only effect in synchronous mode. 0x0: Reserved 0x1: EXMC_CLK period = 2 * HCLK period …… 0xF: EXMC_CLK period = 16 * HCLK period 19:16 Reserved Must be kept at reset value. 15:8 WDSET[7:0] Data setup time...
Page 730 GD32F20x User Manual Bits Fields Description 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0] ALE to RE delay 0x0: ALE to RE delay = 1 * HCLK ……...
Page 731 GD32F20x User Manual NAND flash/PC card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0x0000 0042 for bank1 and bank2, and 0x0000 0043 for bank3 This register has to be accessed by word(32-bit) Reserved Reserved FFEPT...
Page 732 GD32F20x User Manual NAND flash/PC card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) Address offset: 0x48 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFFFF FFFF These operations applicable to common memory space for 16-bit PC Card, CF card and NAND Flash.
Page 733 GD32F20x User Manual …… 0xFE: COMSET = 255 * HCLK 0xFF: COMSET = 256 * HCLK NAND flash/PC card attribute space timing configuration registers (EXMC_NPATCFGx) (x=1, 2, 3) Address offset: 0x4C + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFFFF FFFF It is used for 8-bit accesses to the attribute memory space of the PC Card or to access the NAND Flash for the last address write access if another timing must be applied.
Page 734 GD32F20x User Manual 0xFF: ATTWAIT = 256 * HCLK (+NWAIT active cycles) ATTSET[7:0] Attribute memory setup time Define the time to build address before sending command 0x00: ATTSET = 1 * HCLK …… 0xFE: ATTSET = 255 * HCLK 0xFF: ATTSET = 256 * HCLK PC card I/O space timing configuration register (EXMC_PIOTCFG3) Address offset: 0xB0 Reset value: 0xFFFF FFFF...
Page 735: Sdram Controller Registers
GD32F20x User Manual IOSET[7:0] IO space setup time Define the time to build address before sending command 0x00: IOSET = 1 * HCLK …… 0xFF: IOSET = 256 * HCLK NAND flash ECC registers (EXMC_NECCx) (x=1, 2) Address offset: 0x54+0x20 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) ECC[31:16]...
Page 736 GD32F20x User Manual Reserved PIPED[1:0] BRSTRD SDCLK[1:0] WPEN CL[1:0] SDW[1:0] RAW[1:0] CAW[1:0] Bits Fields Descriptions 31:15 Reserved Must be kept at reset value 14:13 PIPED[1:0] Pipeline delay These bits specify the delay for reading data after CAS latency in HCLK clock cycles.
Page 737 GD32F20x User Manual 0: 2 internal Banks 1: 4 internal Banks SDW[1:0] SDRAM data bus width. These bits specify the SDRAM memory data width. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved RAW[1:0] Row address bit width These bits specify the bit width of a row address.
Page 738 GD32F20x User Manual ..0xF: 16 cycles 23:20 RPD[3:0] Row precharge delay These bits specify the delay between a Precharge command and the next command in SDRAM memory clock cycle unit. 0x0: 1 cycle 0x1: 2 cycles ..0xF: 16 cycles Note: The corresponding bits in the EXMC_SDTR1 register are reserved.
Page 739 GD32F20x User Manual These bits specify the delay from a Self-refresh command to an Activate command in SDRAM memory clock cycle unit. 0x0: 1 cycle 0x1: 2 cycles …… 0xF: 16 cycles LMRD[3:0] Load Mode Register Delay These bits specify the delay between a Load Mode Register command and a Refresh or Active command in SDRAM memory clock cycle unit.
Page 740 GD32F20x User Manual This bit indicates whether the SDRAM Device0 is selected or not. 0: SDRAM Device0 is not selected 1: SDRAM Device0 is selected Device select 1 This bit indicates whether the SDRAM Device1 is selected or not. 0: SDRAM Device1 is not selected 1: SDRAM Device1 is selected CMD[2:0] Command...
Page 741 GD32F20x User Manual This bit field specifies the interval of two successive auto-refresh commands in memory clock cycle unit. ARFITV = (SDRAM refresh period / Number of rows) - 20 Refresh error flag clear The Refresh Error Flag (REIF) in the Status Register will be cleared when this bit is set.
Page 742: Sqpi-Psram Controller Registers
GD32F20x User Manual 1: A refresh error occurred. An interrupt is generated when REIE = 1. SDRAM read sample control register (EXMC_SDRSCTL) Address offset: 0x180 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved SDSC[3:0] Reserved SSCR RSEN...
Page 743 GD32F20x User Manual IDL[1:0] ADRBIT[4:0] Reserved CMDBIT[1:0] Reserved Bits Fields Descriptions Read data sample polarity. 0: Sample data at rising edge(default) 1: Sample data at falling edge. 30:29 IDL[1:0] SPI PSRAM ID Length. 00:64-bit 01:32-bit 10:16-bit 11:8-bit 28:24 ADRBIT[4:0] Bit number of SPI PSRAM address phase. Value Range:1 to 26(default:24) 0x00: reserved 0x01: 1-bit address...
Page 744 GD32F20x User Manual RCMD[15:0] Bits Fields Descriptions RDID Send SPI Read ID Command, command code and mode come from RCMD and RMODE. 30:22 Reserved Must be kept at reset value 21:20 RMODE[1:0] SPI PSRAM Read command mode 00: Not SPI mode 01: SPI mode 10: SQPI mode 11: QPI mode...
Page 745 GD32F20x User Manual 21:20 WMODE[1:0] SPI PSRAM Write command mode 00: Not SPI mode 01: SPI mode 10: SQPI mode 11: QPI mode 19:16 WWAITCYCLE[3:0] SPI Write Wait Cycle number after address phase 15:0 WCMD[15:0] SPI Write Command for AHB write transfer Note: Before write 1 to SC bit, you must ensure it is cleared and after set SC to 1, you must wait SC cleared.
Page 746 GD32F20x User Manual Bits Fields Descriptions 31:0 SIDH[63:32] ID High Data saved for SPI Read ID Command. Note: SIDH[31:0] is valid when IDL=00.
Page 747: Controller Area Network (Can)
GD32F20x User Manual Controller area network (CAN) 26.1. Overview CAN bus (for Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. The Basic Extended CAN, interfaces the CAN network. It supports the CAN protocols version 2.0A and 2.0B.
Page 748: Figure 26-1. Can Module Block Diagram
GD32F20x User Manual  Time Stamp on SOF reception  Time Stamp sent in last two data bytes 26.3. Function overview Figure 26-1. CAN module block diagram shows the CAN block diagram. Figure 26-1. CAN module block diagram Transmit Receive CAN0 CAN0 Tx/Rx mailbox[0..2]...
Page 749: Communication Modes
GD32F20x User Manual Sleep working mode to Normal working mode: Clear IWMOD and SLPWMOD bit in CAN_CTL register. Initial working mode When the options of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode.
Page 750: Figure 26-2. Transmission Register
GD32F20x User Manual Loopback communication mode Loopback communication mode means the sending messages are transferred into the reception FIFOs, the RX pin is disconnected from the CAN network and the TX pin can send messages to the CAN network. Set LCMOD bit in CAN_BT register to enter loopback communication mode or clear it to leave. Loopback communication mode is useful on self-test.
Page 751: Figure 26-3. State Of Transmission Mailbox
GD32F20x User Manual Transmit mailbox state A transmit mailbox can be used when it is free: empty state. If the data is filled in the mailbox, setting TEN bit in CAN_TMIx register to prepare for starting the transmission: pending state. If more than one mailbox is in the pending state, they need schedule the transmission: scheduled state.
Page 752: Figure 26-4. Reception Register
GD32F20x User Manual In the state of transmit, the abort of transmission does not take effect immediately until the transmission is finished. In case of transmission successful, the MTFNERR and MTF in CAN_TSTAT are set and state changes to empty. In case of transmission failed, the state changes to be scheduled and then the abort of transmission can be done immediately.
Page 753: Figure 26-5. 32-Bit Filter
GD32F20x User Manual The number of frames in the receive FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.If at least one frame has been stored in the receive FIFO0. The frame data is placed in the registers (CAN_RFIFOMI0, CAN_RFIFOMP0, CAN_RFIFOMDATA00, CAN_RFIFOMDATA10).
Page 754: Figure 26-6. 16-Bit Filter
GD32F20x User Manual Figure 26-6. 16-bit filter Mask mode In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” (when the bit in mask register is ‘1’) or as “don’t care”...
Page 755: Table 26-1. 32-Bit Filter Number
GD32F20x User Manual is shown in Table 26-1. 32-bit filter number. Table 26-1. 32-bit filter number Filter Filter Filter Data Register Bank Number F0DATA0-32bit-ID F0DATA1-32bit-Mask F1DATA0-32bit-ID F1DATA1-32bit-ID Associated FIFO 28 banks can be associated with FIFO0 or FIFO1. If the bank is associated with FIFO0, the frames passed through the bank will fill the FIFO0.
Page 756: Time-Triggered Communication
GD32F20x User Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active Bank Nunber Bank Nunber Mask F7DATA0[15:0]-16bit- F6DATA0[15:0]-16bit-ID F7DATA0[32:16]-16bit- F6DATA0[32:16]-16bit- Mask Mask F7DATA1[15:0]-16bit- F6DATA1[15:0]-16bit-ID F7DATA1[32:16]-16bit- F6DATA1[32:16]-16bit- Mask Mask F8DATA0[15:0]-16bit- F10DATA0[15:0]-16bit- F8DATA0[32:16]-16bit- F10DATA0[32:16]-16bit- Mask Mask F8DATA1[15:0]-16bit- F10DATA1[15:0]-16bit- F8DATA1[32:16]-16bit- F10DATA1[32:16]-16bit- Mask Mask F9DATA0[15:0]-16bit- F11DATA0[15:0]-16bit- F9DATA0[32:16]-16bit-...
Page 757: Communication Parameters
GD32F20x User Manual communication system is ideal for applications in which the data traffic is of a periodic nature. In this mode, the 16-bit internal counter of the CAN hardware is activated and used to generate the time stamp value stored in the CAN_RFIFOMPx and CAN_TMPx registers for reception and transmission respectively.
Page 758: Figure 26-11. The Bit Time
GD32F20x User Manual Bit segment 1 (BS1): defines the location of the sample point. It includes the Propagation delay segment and Phase buffer segment 1 of the CAN standard. Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network.
Page 759 GD32F20x User Manual 26.3.8. Error flags The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TECNT value, in CAN_ERR register) and a Receive Error Counter (RECNT value, in the CAN_ERR register), which get incremented or decremented according to the error condition.
Page 760 GD32F20x User Manual Transmit interrupt The transmit interrupt can be generated by any of the following conditions and TMEIE bit in CAN_INTEN register will be set:  TX mailbox 0 transmit finished: MTF0 bit in the CAN_TSTAT register is set. ...
Page 761: Register Definition
GD32F20x User Manual 26.4. Register definition CAN0 start address: 0x4000 6400 CAN1 start address: 0x4000 6800 26.4.1. Control register (CAN_CTL) Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit) Reserved SWRST Reserved ABOR RFOD SLPWMOD IWMOD Bits...
Page 762: Status Register (Can_Stat)
GD32F20x User Manual 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable Automatic retransmission 1: Disable Automatic retransmission RFOD Receive FIFO overwrite disable 0: Enable receive FIFO overwrite when the receive FIFO is full and overwrite the FIFO with the incoming frame 1: Disable receive FIFO overwrite when the receive FIFO is full and discard the incoming frame...
Page 763 GD32F20x User Manual LASTRX Last sample value of RX pin Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value...
Page 764: Transmit Status Register (Can_Tstat)
GD32F20x User Manual This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves from normal working mode to initialize working mode, it must wait the current frame transmission or reception completed.
Page 765 GD32F20x User Manual TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty. These bits are the number of the transmit FIFO mailbox in which the frame will be transmitted lastly if all mailboxes are full.
Page 766 GD32F20x User Manual This bit is set while the arbitration lost is occurred. This bit reset by software when write 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit reset by hardware when next transmission starts. MTFNERR1 Mailbox 1 transmit finished and no error This bit is set when the transmission finished and no error.
Page 767: Receive Message Fifo0 Register (Can_Rfifo0)
GD32F20x User Manual 26.4.4. Receive message FIFO0 register (CAN_RFIFO0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RFD0 Receive FIFO0 dequeue This bit is set by the software to start dequeuing a frame from receive FIFO0.
Page 768: Interrupt Enable Register (Can_Inten)
GD32F20x User Manual Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w0 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RFD1 Receive FIFO1 dequeue This bit is set by the software to start dequeuing a frame from receive FIFO1. This bit is reset by the hardware while the dequeuing is done.
Page 769 GD32F20x User Manual 0: Sleep working interrupt disable 1: Sleep working interrupt enable Wakeup interrupt enable 0: Wakeup interrupt disable 1: Wakeup interrupt enable ERRIE Error interrupt enable 0: Error interrupt disable 1: Error interrupt enable 14:12 Reserved Must be kept at reset value ERRNIE Error number interrupt enable 0: Error number interrupt disable...
Page 770: Error Register (Can_Err)
GD32F20x User Manual RFNEIE0 Receive FIFO0 not empty interrupt enable 0: Receive FIFO0 not empty interrupt disable 1: Receive FIFO0 not empty interrupt enable TMEIE Transmit mailbox empty interrupt enable 0: Transmit mailbox empty interrupt disable 1: Transmit mailbox empty interrupt enable 26.4.7.
Page 771: Bit Timing Register (Can_Bt)
GD32F20x User Manual PERR Passive error Whenever the TECNT or RECNT is greater than 127, the bit will be set by the hardware. WERR Warning error Whenever the TECNT or RECNT is greater than or equal to 96, the bit will be set by the hardware.
Page 772: Transmit Mailbox Identifier Register (Can_Tmix) (X=0..2)
GD32F20x User Manual 26.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) Address offset: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (bit0=0) This register has to be accessed by word(32-bit) SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:18] The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13]...
Page 773: Transmit Mailbox Data0 Register (Can_Tmdata0X) (X=0..2)
GD32F20x User Manual TS[15:0] Reserved TSEN Reserved DLENC[3:0] Bits Fields Descriptions 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. 15:9 Reserved Must be kept at reset value TSEN Time stamp enable 0: Time stamp disable 1: Time stamp enable. The TS[15:0] will be transmitted in the DB6 and DB7 in DL This bit is available while the TTC bit in CAN_CTL is set.
Page 774: Transmit Mailbox Data1 Register (Can_Tmdata1X) (X=0..2)
GD32F20x User Manual 26.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) Address offset: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8...
Page 775: Receive Fifo Mailbox Property Register (Can_Rfifompx) (X=0,1)
GD32F20x User Manual EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame 1: Extended format frame Frame type 0: Data frame 1: Remote frame Reserved Must be kept at reset value 26.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) Address offset: 0x1B4, 0x1C4 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit)
Page 776: Receive Fifo Mailbox Data1 Register (Can_Rfifomdata1X) (X=0,1)
GD32F20x User Manual DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 26.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) Address offset: 0x1BC, 0x1CC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB7[7:0] DB6[7:0]...
Page 777: Filter Mode Configuration Register (Can_Fmcfg)
GD32F20x User Manual Reserved HBC1F[5:0] Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value 13:8 HBC1F[5:0] Header bank of CAN1 filter These bits are set and cleared by software to define the first bank for CAN1 filter. Bank0 ~ Bank HBC1F-1 used to CAN0.
Page 778: Filter Associated Fifo Register (Can_Fafifo)
GD32F20x User Manual FLD bit in CAN_FCTL register is set. Reserved FS27 FS26 FS25 FS24 FS23 FS22 FS21 FS20 FS19 FS18 FS17 FS16 FS15 FS14 FS13 FS12 FS11 FS10 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value 27:0 Filter scale 0: Filter x with 16-bit scale...
Page 779: Filter X Data Y Register (Can_Fxdatay) (X=0..27, Y=0,1)
GD32F20x User Manual Reserved FW27 FW26 FW25 FW24 FW23 FW22 FW21 FW20 FW19 FW18 FW17 FW16 FW15 FW14 FW13 FW12 FW11 FW10 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value 27:0 Filter working 0: Filter x working disable 1: Filter x working enable 26.4.22.
Page 780: Ethernet (Enet)
GD32F20x User Manual Ethernet (ENET) 27.1. Overview This chapter describes the Ethernet peripheral module. There is a media access controller (MAC) designed in Ethernet module to support 10/100Mbps interface speed. For more efficient data transfer between Ethernet and memory, a DMA controller is designed in this module.
Page 781: Figure 27-1. Enet Module Block Diagram
GD32F20x User Manual  Two types of wakeup frame detection: LAN remote wakeup frame and AMD Magic PacketTM frames.  Support checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagram.  Support Ethernet frame time stamping for both transmit and receive operation, which describes in IEEE 1588-2008, and 64 bit time stamps are given in each frame’s status.
Page 782: Mac 802.3 Ethernet Packet Description
GD32F20x User Manual The MAC module is connected to the external PHY by MII or RMII through one selection bit (refer to AFIO_PCF0 register). The SMI (Station Management Interface) is used to configure and manage external PHY. Transmitting data module includes: ...
Page 783: Figure 27-2. Mac/Tagged Mac Frame Format
GD32F20x User Manual Figure 27-2 describes the structure of the frame (Basic and Tagged) that includes the following fields: Figure 27-2. MAC/Tagged MAC frame format byte transmission order 46-1500 bytes 2 bytes 7 bytes 6 bytes 1 bytes 6 bytes 4 bytes Frame Destination...
Page 784 GD32F20x User Manual RMII RMII MAC signals Pin configuration default remap default remap AF output push-pull ETH_MDIO MDIO MDIO highspeed (50 MHz) Floating input ETH_MII_COL (reset state) ETH_MII_RX_DV Floating input RX_DV CRS_DV ETH_RMII_CRS_DV (reset state) ETH_MII_RXD0 Floating input RXD0 RXD0 ETH_RMII_RXD0 (reset state) ETH_MII_RXD1...
Page 785: Figure 27-3. Station Management Interface Signals
GD32F20x User Manual 27.3. Function overview 27.3.1. Interface configuration The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet PHY connected through the MII/RMII interface. MII or RMII mode is selected by software and carry on the PHY management through the SMI interface. SMI: Station management interface SMI is designed to access and configure PHY’s configuration.
Page 786: Figure 27-4. Media Independent Interface Signals
GD32F20x User Manual SMI read operation Applications need to operate the ENET_MAC_PHY_CTL register as follows: 1) Set the PHY device address and PHY register address and set PW to 0, so that can select read mode. 2) Set PB bit to start reception. In the process of reception PB is always high until the receiver is complete.
Page 787 GD32F20x User Manual - MII_TX_CLK: clock signal for transmitting data. For the data transmission speed of 10Mbit/s, the clock is 2.5MHz, for the data transmission speed of 100Mbit/s, the clock is 25MHz. - MII_RX_CLK: Clock signal for receiving data. For the data transmission speed of 10Mbit/s, the clock is 2.5MHz, for the data transmission speed of 100Mbit/s, the clock is 25MHz.
Page 788: Figure 27-5. Reduced Media-Independent Interface Signals
GD32F20x User Manual MAC detected an error in the receiving process. The specific error reason needs to cooperate with the state of the MII_RX_DV and the MII_RXD[3:0] data value (see Table 27-3). Table 27-3. Rx interface signal encoding MII_RX_ER MII_RX_DV MII_RXD[3:0] Description 0000 to 1111...
Page 789: Mac Function Overview
GD32F20x User Manual MII/RMII bit transmission order No matter which interface (MII or RMII) is selected, the bit order of transmit/receive is LSB first. The deference between MII and RMII is bit number and sending times. MII is low 4bits first and then high 4bits, but RMII is the lowest 2bits, low 2bits, high 2bits and the highest 2bits.
Page 790 GD32F20x User Manual received the sending instruction, the TxDMA fetches the transmit frames from system memory and pushes them into the TxFIFO, then the data in TxFIFO are poped to MAC for sending on MII/RMII interface. The method of popping is according to the selected TxFIFO mode (Cut- Through mode or Store-and-Forward mode, the specific definition see the next paragraph).For convenient, application can configure automatically hardware calculated CRC and insert it to the FCS domain of Ethernet frame function.
Page 791 GD32F20x User Manual Transmission management of MAC Jabber timer In case of one station occupies the PHY for a long time, there is a jabber timer designed for cutting off the frame whose length is more than 2048 bytes. By default, jabber timer is enabled so when application is transmitting a frames whose byte length is more then 2048, the MAC will only transmit 2048 bytes and drop the last ones.
Page 792 GD32F20x User Manual notify conflict to all other sites. The first condition is triggered by application setting the FLCB/BKPA bit in ENET_MAC_FCTL register. The second condition occurs during receiving frame. When MAC receiver is receiving frame, the byte number of RxFIFO is more and more great.
Page 793 GD32F20x User Manual not reach the configured IGBS bit time in ENET_MAC_CFG register, this transmit frame will be pended unless the counter reach the gap time. But if the second transmit frame presents after the gap time counter has reached the configured gap time, this frame will send immediately.
Page 794 GD32F20x User Manual  TCP/UDP/ICMP payload checksum The checksum offload module processes the IPv4 or IPv6 header (including extension headers) and marks the type of frame (TCP, UDP or ICMP). But when the following frame cases are detected, the checksum offload function will be bypassed and these frames will not be processed by the checksum offload module: 1) Incomplete IPv4 or IPv6 frames 2) IP frames with security features (e.g.
Page 795 GD32F20x User Manual implementing the function. If the FAR bit in the ENET_MAC_FRMF register is '0' (by default), only the frame passed the filter will be received. This function is configured according to the parameters of the application (frame filter register) to filter the destination or/and source address of unicast or multicast frame (The difference between an individual address and a group address is determined by I/G bit in the destination address field) and report the result of the corresponding address filtering.
Page 796: Table 27-4. Destination Address Filtering Table
GD32F20x User Manual ENET_MAC_FRMF register and setting the corresponding HUF or HMF bit in the ENET_MAC_FRMF register. Broadcast frame destination address filter At default, the MAC unconditionally receives the broadcast frames. But when setting BFRMD bit in register ENET_MAC_FRMF, MAC discards all received broadcast frames. Unicast frame source address filter Enable MAC address 1 to MAC address 3 register and set the corresponding SAF bit in the MAC address high register, the MAC compares and filter the source address (SA) field in the...
Page 797: Table 27-5. Source Address Filtering Table
GD32F20x User Manual Frame HPFL BFRM HUF DAIFLT DA filter operation Type Pass all frames Pass on perfect/group filter match and drop PAUSE control frames if PCFRM = Pass on hash filter match and drop PAUSE control frames if PCFRM = 0x Pass on hash or perfect/group filter match and drop PAUSE control frames if PCFRM = 0x...
Page 798 GD32F20x User Manual (RFCEN bit in ENET_MAC_FCTL register is set), the corresponding pause control frame function will be triggered. Whether this filter passed pause frame is forwarded to memory is depending on the PCFRM[1:0] bit in ENET_MAC_FRMF register. Reception process of MAC Received frames will be pushed to the RxFIFO.
Page 799 GD32F20x User Manual Receive flow control In Full-duplex mode, the MAC can detect the pause control frames, and perform it by suspending a certain time which is indicated in pause time field of detected pause control frame and then to transmit data. This function can set by RFCEN bit in ENET_MAC_FCTL register.
Page 800: Mac Statistics Counters: Msc
GD32F20x User Manual RxFIFO will discard the whole frame data and return an overflow status. Also the counter of counting the overflow condition times will plus 1.  If the RxFIFO is configured in Store-and-Forward mode, the MAC can filter and discard all error frames.
Page 801: Wake Up Management: Wum
GD32F20x User Manual  Jabber Timeout When the receiving frame does not appear the following situation, it can be called ‘fine frame’ and MSC reception counters will automatically update:  Alignment error  CRC mismatch(calculated CRC value is different from FSC field value) ...
Page 802: Figure 27-6. Wakeup Frame Filter Register
GD32F20x User Manual Remote wakeup frame filter register Wakeup frame filter register is made up of eight different registers but shared the same register offset address. So the inner pointer points the next filter register when the filter register address is accessed by writing or reading. Whatever operation, write or read, it is strongly recommended to operate eight times sequentially.
Page 803 GD32F20x User Manual Magic packet detection Another wakeup method is detecting Magic Packet frame (see ‘Magic Packet Technology’, Advanced Micro Devices). A Magic Packet frame is a special frame with formed packet solely intended for wakeup purposes. This packet can be received, analyzed and recognized by the Ethernet block and used to trigger a wakeup event.
Page 804: Precision Time Protocol: Ptp
GD32F20x User Manual 1. Wait the current sending frame completes and then reset the TxDMA block by clearing STE bit in ENET_DMA_CTL register. 2. Clear the TEN and REN bit in ENET_MAC_CFG register to disable the MAC’s transmit and receive function. 3.
Page 805: Figure 27-7. System Time Update Using The Fine Correction Method
GD32F20x User Manual Synchronization accuracy The accuracy of time synchronization depends on the following factors: 1) PTP reference clock input period 2) Characteristics of the oscillator (drift) 3) Frequency of the synchronization procedure. System time correction method The 64-bit PTP system time update by the PTP input reference clock. The PTP system time is used as the source to record transmission/reception frame’s timestamp.
Page 806 GD32F20x User Manual Assuming the accuracy of the system time update circuit required to achieve 20ns, which means the frequency of update is 50MHz. If the reference clock of HCLK is 75MHz, the frequency ratio is calculated as 75/50, result is 1.5. Hence, the addend (TMSA bit in ENET_PTP_TSADDEND register) value to be set is 2 /1.5, which is equal to 0xAAAA AAAA.
Page 807 GD32F20x User Manual time after this bit is set from reset, application must initialize the timestamp counter at first. Initialization steps as follow: 1. Setting bit 9 in the ENET_MAC_INTMSK register to mask the timestamp trigger interrupt 2. Setting bit 0 in the ENET_PTP_TSCTL register to enable timestamp function 3.
Page 808: Dma Controller Description
GD32F20x User Manual Transmission and reception of frames with the PTP feature After enabled the IEEE 1588 (PTP) timestamp function, timestamp is recorded when the frame’s SFD field is outputting from the MAC or the MAC receives a frame’s SFD field. Each transmitted frame can be marked in TxDMA descriptor to indicate whether a timestamp should be captured or not.
Page 809: Figure 27-8. Descriptor Ring And Chain Structure
GD32F20x User Manual maximum of two buffers. The value of the buffer 2 can be programmed to the second data address or the next descriptor address which is determined by the configured descriptor table type: Ring or Chain. Buffer space only contains frame data which are located in host’s physical memory space.
Page 810 GD32F20x User Manual Alignment rule for data buffer address The DMA controller supports all alignment types: byte alignment, half-word alignment and word alignment. This means application can configure the buffer address to any address. But during the operation of the DMA controller, access address is always word align and is different between write and read access.
Page 811 GD32F20x User Manual to be large enough to store the whole frame, the FSG and the LSG bit are set in the same descriptor. The actual frame length FRML can be read from RDES0. So application can calculate the left unused buffer space. The RxDMA always uses a new descriptor to receive the start of next frame.
Page 812 GD32F20x User Manual TxDMA configuration Operate on second frame in buffer When OSF bit in ENET_DMA_CTL is reset, the order of the transmitting is follows: the first is reading transmit descriptor, followed by reading data from memory and writing to FIFO, then sending frame data on interface through MAC and last wait frame data transmitting complete and writing back transmitting status.
Page 813 GD32F20x User Manual TxDMA operation mode (B): OSF The TxDMA controller supports transmitting two frames without waiting status write back of the first frame, this mode is called operation on second frame (OSF). When the frequency of system is much faster than the frequency of the MAC interface (10Mbit/s or 100Mbit/s), the OSF mode can improve the sending efficiency.
Page 814 GD32F20x User Manual The Preamble and SFD are automatically generated by the MAC, so the application only need store the DA, SA, QTAG(if needed), LT, DATA, DATA, PAD(if needed), FCS(if needed) parts. If the frame needs padding which means PAD and FCS parts are not stored in buffer, then application can configure the MAC to generate the PAD and FCS.
Page 815: Figure 27-9. Transmit Descriptor
GD32F20x User Manual Note: When a frame is described by more than one descriptor, only the control bits of the first descriptor are accept by TxDMA controller (except INTC). But the status and timestamp (if enabled) are written back to the last descriptor. Figure 27-9.
Page 816 GD32F20x User Manual DCRC Disable CRC bit This is valid only when the first segment (TDES0[28]) is set. 0: The MAC automatic append a CRC to the end of the transmitted frame 1: The MAC does not append a CRC to the end of the transmitted frame DPAD Disable adding pad bit This is valid only when the first segment (TDES0[28]) is set.
Page 817 GD32F20x User Manual IPHE IP header error bit IP header error occurs when any case of below happen: IPv4 frames: 1) The header length field has a value less than 0x5. 2) The header length field value in transmitting IPv4 frame is mismatch with the number of header bytes 3) The version field value does not match the length/type field value IPv6 frames:...
Page 818 GD32F20x User Manual 1:A loss of carrier occurred during frame transmission No carrier bit 0: PHY carrier sense signal is active 1: The carrier sense signal from the PHY was not asserted during transmission Late collision bit If a collision occurs when 64 bytes (including preamble and SFD) has already transferred, this situation called late collision.
Page 819 GD32F20x User Manual 1:The MAC is deferred before transmission  TDES1: Transmit descriptor word 1 Reserved TB2S[12:0] Reserved TB1S[12:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:16 TB2S[12:0] Transmit buffer 2 size bits These bits indicate byte size of the second data buffer. This field is not valid if the TCHM bit (TDES0[20]) is set.
Page 820 GD32F20x User Manual TB2AP/TTSH[15:0] Bits Fields Descriptions 31:0 TB2AP/TTSH[31:0] Transmit buffer 2 address pointer (or next descriptor address) / Transmit frame timestamp high 32-bit value bits Before transmitting frame, application must configure these bits for transmit buffer 2 address (TB2AP) or the next descriptor address which is decided by descriptor type is ring or chain.
Page 821 GD32F20x User Manual 2) The next descriptor’s DAV bit is set. The RxDMA controller closes current descriptor by resetting DAV bit and operation goes to Step 4. If IEEE 1588 time stamping function is enabled, the RxDMA controller writes the time stamp value (if receiving frame meets the configured time stamping condition) to the current descriptor’s RDES2 and RDES3.
Page 822: Figure 27-10. Receive Descriptor
GD32F20x User Manual frame, if any one of the below cases occurs the MAC can discard the received frame data in RxFIFO and the RxDMA controller will not forward these data: 1) The received frame bytes is less than 64. 2) Collision occurred during frame receiving. 3) The premature termination for the receiving frame.
Page 823 GD32F20x User Manual  RDES0: Receive descriptor word 0 DAFF FRML[13:0] ERRS DERR SAFF LERR OERR VTAG FDES LDES IPHERR/TSV FRMT RWDT RERR DBERR CERR PCERR/EXSV Bits Fields Descriptions Descriptor available bit This bit indicates the DMA controller can use this descriptor. The DMA clears this bit either when it completes the frame reception or when the buffers in this descriptor are full 0: The descriptor is owned by the CPU...
Page 824 GD32F20x User Manual REDS0[7] = 1, REDS0[5] = 1 and REDS0[0] = 0: header checksum error REDS0[7] = 1, REDS0[5] = 1 and REDS0[0] = 1: both header and payload checksum errors DERR Descriptor error bit This field is valid only when the LDES (RDES0[8]) is set. When the current buffer cannot hold current received frame and the next descriptor’s DAV bit is reset, the descriptor error occurs.
Page 825: Table 27-6. Error Status Decoding In Rdes0, Only Used For Normal Descriptor
GD32F20x User Manual Late collision bit This bit indicates a collision occurs after 64 bytes have been received This bit only valid in Half-duplex mode. 0: No late collision occurred 1: Late collision has occurred FRMT Frame type bit This bit is not valid for Runt frames less than 14 bytes. 0: The received frame is an IEEE802.3 frame 1: The receive frame is an Ethernet-type frame (the LT field is greater than or equal to 0x0600)
Page 826 GD32F20x User Manual Bit 7: Bit 5: Bit 0: Frame status IPHERR FRMT PCERR IEEE 802.3 normal frame (Length field value is less than 0x0600 and not tagged) IPv4 or IPv6 frame, no header checksum error, payload checksum is bypassed because of unsupported payload type IPv4 or IPv6 frame, checksum checking pass IPv4 or IPv6 frame, payload checksum error.
Page 827 GD32F20x User Manual The second buffer size in bytes. The buffer size must be a multiple of 4. This field is ignored if RCHM (RDES1[14]) is set RERM Receive end of ring mode bit This bit indicates the final descriptor in table is arrived and the next descriptor address is automatically set to the configured start descriptor address.
Page 828: Example For A Typical Configuration Flow Of Ethernet
GD32F20x User Manual RB2AP/RTSH[31:16] RB2AP/RTSH[15:0] Bits Fields Descriptions 31:0 RB2AP/RTSH[31:0] Receive buffer 2 address pointer (next descriptor address) / Receive frame timestamp high 32-bit value bits These bits are designed for two different functions: buffer address pointer or next descriptor address (RB1AP) or timestamp high 32-bit value (RTSH). RB2AP: Before fetching this descriptor by RxDMA controller, these bits are configured to the buffer 2 address (RCHM=0) or the next descriptor address (RCHM=1) by application.
Page 829: Ethernet Interrupts
GD32F20x User Manual not, support 10M/100Mbit speed or not, and so on). Based on supported mode of external PHY, configure ENET_MAC_CFG register consistent with PHY register.  Initialize the DMA in Ethernet module for transaction Configure the ENET_DMA_BCTL, ENET_DMA_RDTADDR, ENET_DMA_TDTADDR, ENET_DMA_CTL registers to initialize the DMA module.
Page 830: Figure 27-11. Mac Interrupt Scheme
GD32F20x User Manual normal operation interrupts and the second vector is made up of WUM events for wakeup which is mapped to the EXTI line 19. All of the MAC and DMA controller interrupt are connected to the first interrupt vector. The description for the MAC interrupt and DMA controller interrupt are showed behind.
Page 831: Figure 27-12. Ethernet Interrupt Scheme
GD32F20x User Manual Figure 27-12. Ethernet interrupt scheme TBUIE NISE Normal Interrupt ERIE Ethernet MSCI Interrupt WUMI TMSTI FBEIE Abnormal Interrupt TJTIE TPSIE RBUIE ROIE AISE RPSIE TUIE ETIE RWTIE...
Page 832: Register Definition
GD32F20x User Manual 27.4. Register definition Byte (8-bit) access, half word (16-bit) access and word (32-bit) access are all supported for application. ENET start address: 0x4002 8000 27.4.1. MAC configuration register (ENET_MAC_CFG) Address offset: 0x0000 Reset value: 0x0000 8000 This register configures the operation mode of the MAC. It also configures the MAC receiver and MAC transmitter operating mode.
Page 833 GD32F20x User Manual 0x5: 56 bit times(For Half-duplex, must be reserved) 0x6: 48 bit times(For Half-duplex, must be reserved) 0x7: 40 bit times(For Half-duplex, must be reserved) Carrier sense disable bit 0: The MAC transmitter generates carrier sense error and aborts the transmission 1: The MAC transmitter ignores the MII CRS signal during frame transmission in Half-duplex mode.
Page 834: Mac Frame Filter Register (Enet_Mac_Frmf)
GD32F20x User Manual 1 slot time is equal to 512 bit times. This delay time (dt) is a random integer number calculated by following formula : 0≤dt <2 0x0: k = min (n, 10) 0x1: k = min (n, 8) 0x2: k = min (n, 4) 0x3: k = min (n, 1), n = number of times for retransmission attempt...
Page 835 GD32F20x User Manual 0: Only the frame passed the filter can be forwarded to application. 1: All received frame are forwarded to application. But filter result will also be updated to receive descriptor status. 30:11 Reserved Must be kept at reset value HPFLT Hash or perfect filter bit 0: If the HUF or HMF bit is set, only frames that match the hash filter are passed...
Page 836: Mac Hash List High Register (Enet_Mac_Hlh)
GD32F20x User Manual 1: Inverse DA filtering result Hash multicast filter bit 0: The filter uses perfect mode for filtering multicast frame. 1: The filter uses hash mode for filtering multicast frame Hash unicast filter bit 0: The filter uses perfect mode for filtering unicast frame 1: The filter uses hash mode for filtering unicast frame Promiscuous mode bit This bit can make the filter bypassed which means all received frames are thought...
Page 837: Mac Phy Control Register (Enet_Mac_Phy_Ctl)
GD32F20x User Manual 31:0 HLL[31:0] Hash list low bits These bits take the low 32-bit value of hash list 27.4.5. MAC PHY control register (ENET_MAC_PHY_CTL) Address offset: 0x0010 Reset value: 0x0000 0000 Reserved PA[4:0] PR[4:0] Reserved CLR[2:0] rc_w1 Bits Fields Descriptions 31:16 Reserved...
Page 838: Mac Mii Data Register (Enet_Mac_Phy_Data)
GD32F20x User Manual 27.4.6. MAC MII data register (ENET_MAC_PHY_DATA) Address offset: 0x0014 Reset value: 0x0000 0000 Reserved PD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PD[15:0] PHY data bits For reading operation, these bits contain the data from external PHY. For writing operation, these bits contain the data will be sent to external PHY.
Page 839: Mac Flow Control Threshold Register (Enet_Mac_Fcth)
GD32F20x User Manual These bits configure the threshold of the pause timer for retransmitting frames automatically. Application must make sure the low threshold bits are greater than 0 and less than configured pause time. The low threshold calculation formula is PTM- PLTS.
Page 840: Mac Vlan Tag Register (Enet_Mac_Vlt)
GD32F20x User Manual Reset value: 0x0000 0015 Reserved Reserved RFD[2:0] Reserved RFA[2:0] Bits Fields Descriptions 31:7 Reserved Must be kept at reset value RFD[2:0] Threshold of deactive flow control This field configures the threshold of the deactive flow control. The value should always be less than the Threshold of active flow control value configured in bits[2:0].
Page 841: Figure 27-13. Wakeup Frame Filter Register
GD32F20x User Manual the following 2 bytes (the 15 and 16 byte) are compared with the VLAN tag. Reserved VLTC VLTI[15:0] Bits Fields Descriptions 31:17 Reserved Must be kept at reset value VLTC 12-bit VLAN tag comparison bit This bit selects 12 or 16 bit VLAN tag for comparison. 0: All 16 bits (the 15 and 16 byte) of the VLAN tag in received frame are used for...
Page 842: Mac Wakeup Management Register (Enet_Mac_Wum)
GD32F20x User Manual Wakeup frame filter Byte Mask of Filter-0 reg0 Wakeup frame filter Byte Mask of Filter-1 reg1 Wakeup frame filter Byte Mask of Filter-2 reg2 Wakeup frame filter Byte Mask of Filter-3 reg3 Wakeup frame filter Filter 3 Filter 2 Filter 1 Filter 0...
Page 843: Mac Interrupt Flag Register (Enet_Mac_Intf)
GD32F20x User Manual 1:The wakeup event was generated due to reception of a wakeup frame MPKR Magic packet received bit This bit is cleared when this register is read 0:Has not received the Magic Packet frame 1:The wakeup event was generated by the reception of a Magic Packet frame Reserved Must be kept at reset value WFEN...
Page 844: Mac Interrupt Mask Register (Enet_Mac_Intmsk)
GD32F20x User Manual MSCR MSC receive status bit 0: All the bits in register ENET_MSC_RINTF are cleared 1: An interrupt is generated in the ENET_MSC_RINTF register MSC status bit This bit is logic ORed from MSCT and MSCR bit. 0: Both MSCT and MSCR bits in this register are low 1: Any of bit 6 (MSCT) or bit 5 (MSCR) is set high WUM status bit This bit is logic ORed from WUFR and MPKR bit in ENET_MAC_WUM register.
Page 845: Mac Address 0 Low Register (Enet_Mac_Addr0L)
GD32F20x User Manual Reset value: 0x8000 FFFF Reserved ADDR0H[15:0] Bits Fields Descriptions Always read 1 and must be kept 30:16 Reserved Must be kept at reset value 15:0 ADDR0H[15:0] MAC address0 high16-bit These bits contain the high 16-bit (bit 47 to 32) of the 6-byte MAC address0. These bits are used for address filtering in frame reception and address inserting in pause frame transmitting during transmit flow control.
Page 846: Mac Address 1 Low Register (Enet_Mac_Addr1L)
GD32F20x User Manual ADDR1H[15:0] Bits Fields Descriptions Address filter enable bit 0: The address filter ignores the MAC address1 for filtering 1: The address filter uses the MAC address1 for perfect filtering Source address filter bit 0: The MAC address1[47:0] is used to comparing with the DA field of the received frame 1: The MAC address1[47:0] is used to comparing with the SA field of the received frame...
Page 847: Mac Address 2 High Register (Enet_Mac_Addr2H)
GD32F20x User Manual This field contains the low 32-bit of the 6-byte MAC address1 27.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) Address offset: 0x0050 Reset value: 0x0000 FFFF MB[5:0] Reserved ADDR2H[15:0] Bits Fields Descriptions Address filter enable bit 0:The address filter ignores the MAC address2 for filtering 1:The address filter uses the MAC address2 for perfect filtering Source address filter bit 0:The MAC address2[47:0] is used to comparing with the DA fields of the received...
Page 848: Mac Address 3 High Register (Enet_Mac_Addr3H)
GD32F20x User Manual ADDR2L[31:16] ADDR2L[15:0] Bits Fields Descriptions 31:0 ADDR2L[31:0] MAC address2 low 32-bit This field contains the low 32-bit of the 6-byte MAC address2 27.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) Address offset: 0x0058 Reset value: 0x0000 FFFF MB[5:0] Reserved ADDR3H[15:0] Bits...
Page 849: Mac Address 3 Low Register (Enet_Mac_Addr3L)
GD32F20x User Manual MB[0]: ENET_MAC_ADDR3L [7:0] 23:16 Reserved Must be kept at reset value 15:0 ADDR3H[15:0] MAC address3 high 16-bit This field contains the high 16-bit (bit 47 to 32) of the 6-byte MAC address3 27.4.21. MAC address 3 low register (ENET_MAC_ADDR3L) Address offset: 0x005C Reset value: 0xFFFF FFFF ADDR3L[31:16]...
Page 850: Msc Receive Interrupt Flag Register (Enet_Msc_Rintf)
GD32F20x User Manual 1: The MSC counters are reset to zero after read them CTSR Counter stop rollover bit 0: The counters roll over to zero after they reached the maximum value 1: The counters do not roll over to zero after they reached the maximum value Counter reset bit Cleared by hardware 1 clock after set.
Page 851: Msc Receive Interrupt Mask Register (Enet_Msc_Rintmsk)
GD32F20x User Manual Reserved Reserved rc_r TGFMSC TGFSC Reserved rc_r rc_r Bits Fields Descriptions 31:22 Reserved Must be kept at reset value Transmitted good frames bit 0: Good frame transmitted counter is less than half of the maximum value 1: Good frame transmitted counter reaches half of the maximum value 20:16 Reserved Must be kept at reset value...
Page 852: Msc Transmit Interrupt Mask Register (Enet_Msc_Tintmsk)
GD32F20x User Manual 31:18 Reserved Must be kept at reset value RGUFIM Received good unicast frames interrupt mask bit 0: Unmask the interrupt when the RGUF bit is set 1: Mask the interrupt when RGUF bit is set 16:7 Reserved Must be kept at reset value RFAEIM Received frames alignment error interrupt mask bit...
Page 853: Msc Transmitted Good Frames After A Single Collision Counter Register
GD32F20x User Manual 13:0 Reserved Must be kept at reset value 27.4.27. MSC transmitted good frames after a single collision counter register (ENET_MSC_SCCNT) Address offset: 0x014C Reset value: 0x0000 0000 This register counts the number of successfully transmitted frames after a single collision in Half-duplex mode.
Page 854: Msc Transmitted Good Frames Counter Register (Enet_Msc_Tgfcnt)
GD32F20x User Manual 27.4.29. MSC transmitted good frames counter register (ENET_MSC_TGFCNT) Address offset: 0x0168 Reset value: 0x0000 0000 This register counts the number of good frames transmitted. TGF[31:16] TGF[15:0] Bits Fields Descriptions 31:0 TGF[31:0] Transmitted good frames counter bits These bits count the number of transmitted good frames 27.4.30.
Page 855: Ptp Time Stamp Control Register (Enet_Ptp_Tsctl)
GD32F20x User Manual RFAER[31:16] RFAER[15:0] Bits Fields Descriptions 31:0 RFAER[31:0] Received frames alignment error counter bits These bits count the number of receive frames with alignment error 27.4.32. received good unicast frames counter register (ENET_MSC_RGUFCNT) Address offset: 0x01C4 Reset value: 0x0000 0000 This register counts the number of good unicast frames received.
Page 856: Ptp Subsecond Increment Register (Enet_Ptp_Ssinc)
GD32F20x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value TMSARU Time stamp addend register update bit This bit is cleared when the update is completed. This register bit must be read as zero before application set it. 0: The timestamp addend register’s contents are not updated to the PTP block for fine correction 1: The timestamp addend register’s contents are updated to the PTP block for fine...
Page 857: Ptp Time Stamp High Register (Enet_Ptp_Tsh)
GD32F20x User Manual Reserved Reserved STMSSI[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value STMSSI[7:0] System time subsecond increment bits In every update operation, these bits are added to the subsecond value of system time. 27.4.35. PTP time stamp high register (ENET_PTP_TSH) Address offset: 0x0708 Reset value: 0x0000 0000 STMS[31:16]...
Page 858: Ptp Time Stamp Update High Register (Enet_Ptp_Tsuh)
GD32F20x User Manual 0: Time value is positive 1: Time value is negative 30:0 STMSS[30:0] System time subseconds bits These bits show the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns. 27.4.37. PTP time stamp update high register (ENET_PTP_TSUH) Address offset: 0x0710 Reset value: 0x0000 0000...
Page 859: Ptp Time Stamp Addend Register (Enet_Ptp_Tsaddend)
GD32F20x User Manual 0: Timestamp update value is added to system time 1: Timestamp update value is subtracted from system time 30:0 TMSUSS[30:0] Timestamp update subsecond bits These bits are used for initializing or adding/subtracting to subsecond of the system time 27.4.39.
Page 860: Ptp Expected Time Low Register (Enet_Ptp_Etl)
GD32F20x User Manual 27.4.41. PTP expected time low register (ENET_PTP_ETL) Address offset: 0x0720 Reset value: 0x0000 0000 ETSL[31:16] ETSL[15:0] Bits Fields Descriptions 31:0 ETSL[31:0] Expected time low bits These bits store the expected target nanosecond time (signed). 27.4.42. DMA bus control register (ENET_DMA_BCTL) Address offset: 0x1000 Reset value: 0x0000 2101 Reserved...
Page 861 GD32F20x User Manual 1: The RxDMA uses the RXDP[5:0] bits as burst length while the PGBL[5:0] is used by TxDMA 22:17 RXDP[5:0] RxDMA PGBL bits If UIP=0, these bits are not valid. Only when UIP=1, these bits is configured for the maximum number of beats to be transferred in one RxDMA transaction.
Page 862: Dma Transmit Poll Enable Register (Enet_Dma_Tpen)
GD32F20x User Manual When DPSL value equals zero, the descriptor table is taken as contiguous by the DMA, in ring mode DMA arbitration bit This bit indicates the arbitration mode between RxDMA and TxDMA. 0: Round-robin mode and DMA access priority is given in RTPR 1: Fixed mode.
Page 863: Dma Receive Descriptor Table Address Register (Enet_Dma_Rdtaddr)
GD32F20x User Manual descriptor table. Writing to this register makes the RxDMA controller exit suspend state. RPE[31:16] rw_wt RPE[15:0] rw_wt Bits Fields Descriptions 31:0 RPE[31:0] Receive poll enable bits Writing to this register with any value makes DMA read the current descriptor address which is indicated in ENET_DMA_CRDADDR register.
Page 864: Dma Status Register (Enet_Dma_Stat)
GD32F20x User Manual in the physical memory space and must be word-aligned. This register can only be written when TxDMA controller is in stop state. Before starting TxDMA transmission process, this register must be configured correctly. STT[31:16] STT[15:0] Bits Fields Descriptions 31:0 STT[31:0]...
Page 865 GD32F20x User Manual 0: WUM event has not occurred 1: WUM event has occurred MSC status bit This bit indicates a MSC event occurred. It is cleared when all of event sources are cleared. If the corresponding interrupt mask bit is reset, an interrupt is generated. 0: MSC event has not occurred 1: MSC event has occurred Reserved...
Page 866 GD32F20x User Manual TS (ENET_DMA_STAT [0]): Transmit interrupt TBU (ENET_DMA_STAT [2]): Transmit buffer unavailable RS (ENET_DMA_STAT [6]): Receive interrupt ER (ENET_DMA_STAT [14]): Early receive interrupt Note: Each time when this bit is set, application must cleared its source bit by writing 1 to that bit.
Page 867: Dma Control Register (Enet_Dma_Ctl)
GD32F20x User Manual 0: The DAV bit in fetched next receive descriptor is set 1: The DAV bit in fetched next receive descriptor is reset and RxDMA enters suspend state. Receive status bit 0: Frame reception has not completed 1: Frame reception has completed Transmit underflow status bit 0: Underflow error has not occurred during frame transmission 1: The TxFIFO encountered an underflow error during frame transmission and...
Page 868 GD32F20x User Manual TTHC[1:0] Reserved FERF Reserved RTHC[1:0] Reserved Bits Fields Descriptions 31:27 Reserved Must be kept at reset value DTCERFD Dropping of TCP/IP checksum error frames disable bit 0: All error frames will be dropped when FERF=0 1: The received frame with only payload error but no other errors will not be dropped. RSFD Receive Store-and-Forward bit 0: The RxFIFO operates in Cut-Through mode.
Page 869 GD32F20x User Manual 0x4: 40 0x5: 32 0x6: 24 0x7: 16 Start/stop transmission enable bit 0: The TxDMA controller will enter stop state after transmitting complete if the current frame is being transmitted. After complete transmitting, the next descriptor address will become current descriptor address for the address pointer. If the TxDMA controller is in suspend state, reset this bit make the controller entering stop state.
Page 870: Dma Interrupt Enable Register (Enet_Dma_Inten)
GD32F20x User Manual Operate on second frame bit 0: The TxDMA controller process the second transmit frame after the status of the first frame is written back to descriptor 1: The TxDMA controller process the second transmit frame after pushed all first frame data into TxFIFO but before the status of the first frame is written back to descriptor Start/stop receive enable bit...
Page 871 GD32F20x User Manual TBU (ENET_DMA_STAT [2]): Transmit buffer unavailable RS (ENET_DMA_STAT [6]): Receive interrupt ER (ENET_DMA_STAT [14]): Early receive interrupt Abnormal interrupt summary enable bit 0: An abnormal interrupt is disabled. 1: An abnormal interrupt is enabled This bit enables the following bits: TPS (ENET_DMA_STAT [1]):Transmit process stopped TJT (ENET_DMA_STAT [3]):Transmit jabber timeout RO (ENET_DMA_STAT [4]): Receive FIFO overflow...
Page 872 GD32F20x User Manual 0: The underflow interrupt is disabled 1: The underflow interrupt is enabled ROIE Receive overflow interrupt enable bit 0: The overflow interrupt is disabled 1: The overflow interrupt is enabled TJTIE Transmit jabber timeout interrupt enable bit 0: The transmit jabber timeout interrupt is disabled 1: The transmit jabber timeout interrupt is enabled TBUIE...
Page 873 GD32F20x User Manual These bits indicate the number of frames dropped by RxFIFO Reserved Must be kept at reset value 15:0 MSFC[15:0] Missed frames by the controller bits These bits indicate the number of frames missed by the RxDMA controller because of the unavailable receive buffer.
Page 874: Dma Current Transmit Buffer Address Register (Enet_Dma_Ctbaddr)
GD32F20x User Manual Bits Fields Descriptions 31:0 RDAP[31:0] Receive descriptor address pointer bits These bits are automatically updated by RxDMA controller during operation. 27.4.53. DMA current transmit buffer address register (ENET_DMA_CTBADDR) Address offset: 0x1050 Reset value: 0x0000 0000 This register points to the current transmit buffer address being read by the TxDMA controller. TBAP[31:16] TBAP[15:0] Bits...
Page 875: Universal Serial Bus Full-Speed Interface (Usbfs)
GD32F20x User Manual Universal serial bus full-speed interface (USBFS) The USBFS is available on GD32F205 and GD32F207 series. 28.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution for portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol).
Page 876: Figure 28-1. Usbfs Block Diagram
GD32F20x User Manual 28.3. Block diagram Figure 28-1. USBFS block diagram interrupts Register AHB Slave Device bus Host Port control Control Data UTMI FIFO USB FS Transcation Scheduler Control VBUS USB Clock USB Clock Domain 48MHz 28.4. Signal description Table 28-1. USBFS signal description I/O port Type Description...
Page 877: Figure 28-2. Connection With Host Or Device Mode
GD32F20x User Manual they could be controlled by USBFS automatically according to the current mode (host, device or OTG mode) and connection status. A typical connection is shown in Figure 28-2. Connection with host or device mode. Figure 28-2. Connection with host or device mode 5V Power Supply GPIO...
Page 878: Figure 28-3. Connection With Otg Mode
GD32F20x User Manual Figure 28-3. Connection with OTG mode 5V Power GPIO Supply VBus VBUS 28.5.2. USB host function USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state.
Page 879 GD32F20x User Manual detected and will trigger a disconnection flag after a disconnection event. PRST bit in USBFS_HPCS register is used for USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset. This bit only takes effect when port is at connected or enabled state.
Page 880: Usb Device Function
GD32F20x User Manual transaction schedule. A request entry in a request queue described above may represent a USB transaction request or a channel operation request. Application needs to write packet into data FIFO via AHB bus if it wants to start an OUT transaction on USB bus.
Page 881: Otg Function Overview
GD32F20x User Manual change on data lines for 3ms. When USB device is in suspend state, most of its clocks are closed to save power. The USB host is able to wake up the suspended device by generating a resume signal on USB bus. When USBFS detects the resume signal, the WKUPIF flag in USBFS_GINTF register will be set and the USBFS wakeup interrupt will be triggered.
Page 882: Data Fifo
GD32F20x User Manual Since On-The-Go devices have a Micro-AB receptacle, an On-The-Go device can be a host/device by default, depending on which type of plug (Micro-A plug for host, Micro-B plug for device) is inserted. By utilizing the Host Negotiation Protocol (HNP), an On-The-Go B- Device, which is the default device, may request to be a host.
Page 883: Figure 28-5. Host Mode Fifo Space In Sram
GD32F20x User Manual Figure 28-5. HOST mode FIFO space in SRAM USBFS provides a special register area for the internal data FIFO reading and writing. Figure 28-6. Host mode FIFO access register mapping describes the register memory area that the data FIFO can access. The addresses in the figure are addressed in bytes. Each channel has its own FIFO access register space, although all non-periodic channels share the same FIFO and all the periodic channels also share the same FIFO.
Page 884: Figure 28-7. Device Mode Fifo Space In Sram
GD32F20x User Manual of 32-bit words. Figure 28-7. Device mode FIFO space in SRAM Start: 0x00 Rx FIFO RXFD IEPTX0RSAR[15:0] Tx FIFO0 IEPTX0FD IEPTX1RSAR[15:0] Tx FIFO1 IEPTX1FD IEPTX3RSAR[15:0] Tx FIFO3 IEPTX3FD End: 0x13F USBFS provides a special register area for the internal data FIFO reading and writing. Figure 28-8.
Page 885 GD32F20x User Manual Host mode Global register initialization sequence Program USBFS_GAHBCS register according to application’s demand, such as the Tx FIFO’s empty threshold, etc. GINTEN bit should be kept cleared at this time. Program USBFS_GUSBCS register according to application’s demand, such as the operation mode (host, device or OTG) and some parameters of OTG and USB protocols.
Page 886 GD32F20x User Manual USBFS will generate a channel disable request entry in request queue after the register setting operation. When the request entry reaches the top of request queue, it will be processed by USBFS immediately: For OUT channels, the specified channel will be disabled immediately. Then, a CH flag will be generated and the CEN and CDIS bits will be cleared by USBFS.
Page 887 GD32F20x User Manual this request entry. If bus time for the transaction indicated by the request entry is enough, USBFS starts the OUT transaction on USB bus. When the OUT transaction indicated by the request entry has been finished on USB bus, PCNT in USBFS_HCHxLEN register is decreased by 1.
Page 888 GD32F20x User Manual Program USBFS_DIEPxLEN or USBFS_DOEPxLEN register. PCNT is the number of packets in a transfer and TLEN is the total bytes number of all the transmitted or received packets in a transfer. For IN endpoint：If PCNT=1, the single packet’s size is equal to TLEN. If PCNT>1, the former PCNT-1 packets are considered as max-packet-length packets whose size are defined by MPL field in USBFS_DIEPxCTL register, and the last packet ’s size is calculated based on PCNT, TLEN and MPL.
Page 889: Table 28-2. Usbfs Global Interrupt
GD32F20x User Manual the status flags report the transaction result. After all the data packets in a transfer are successfully received on USB bus, USBFS pushes a TF status entry into the Rx FIFO on top of the last packet data. Thus, after reading and popping all the received data packet, the TF status entry is read.
Page 890 GD32F20x User Manual Interrupt Flag Description Operation Mode Early suspend Device mode Global OUT NAK effective GONAK Device mode Global IN Non-Periodic NAK effective GNPINAK Device mode Non-Periodic Tx FIFO empty interrupt NPTXFEIF Host Mode flag Rx FIFO non-empty interrupt flag RXFNEIF Host or device mode Start of frame...
Page 891: Register Definition
GD32F20x User Manual 28.7. Register definition USBFS base address: 0x5000 0000 28.7.1. Global control and status registers Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 892 GD32F20x User Manual Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes. 15:12 Reserved Must be kept at reset value.
Page 893 GD32F20x User Manual SRPS SRP success flag This bit is set by the core when SRP succeeds, and this bit is cleared when SRPREQ bit is set. 0: SRP failure 1: SRP success Note: Only accessible in device mode. Global OTG interrupt flag register (USBFS_GOTGINTF) Address offset: 0x0004 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 894 GD32F20x User Manual Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP. Note: Accessible in both device and host modes. Reserved Must be kept at reset value.
Page 895 GD32F20x User Manual 1: NPTXFEIF will be triggered when the non-periodic Tx FIFO is completely empty 6：1 Reserved Must be kept at reset value. GINTEN Global interrupt enable 0: Global interrupt is not enabled. 1: Global interrupt is enabled. Note: Accessible in both device and host modes. Global USB control and status register (USBFS_GUSBCS) Address offset: 0x000C Reset value: 0x0000 0A80...
Page 896 GD32F20x User Manual the force bit. Note: Accessible in both device and host modes. 28:14 Reserved Must be kept at reset value. 13:10 UTT[3:0] USB turnaround time Turnaround time in PHY clocks. Note: Only accessible in device mode. HNPCEN HNP capability enable Controls whether the HNP capability is enabled 0: HNP capability is disabled 1: HNP capability is enabled...
Page 897 GD32F20x User Manual Bits Fields Descriptions AHBMIDL AHB master idle, this bit is always 1 for both device and host mode 30:11 Reserved Must be kept at reset value. 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set. Host Mode: 00000: Only non-periodic Tx FIFO is flushed 00001: Only periodic Tx FIFO is flushed...
Page 898 GD32F20x User Manual operation on USBFS. Note: Accessible in both device and host modes. CSRST Core soft reset Resets the AHB and USB clock domains circuits, as well as most of the registers. Global interrupt flag register (USBFS_GINTF) Address offset: 0x0014 Reset value: 0x0400 0021 This register has to be accessed by word (32-bit) rc_w1...
Page 899 GD32F20x User Manual empty. The threshold is determined by the periodic Tx FIFO empty level bit (PTXFTH) in the USBFS_GAHBCS register. Note: Only accessible in host mode. HCIF Host channels interrupt flag Set by USBFS when one of the channels in host mode has raised an interrupt. First read USBFS_ HACHINT register to get the channel number, and then read the corresponding USBFS_HCHxINTF register to get the flags of the channel that cause the interrupt.
Page 900 GD32F20x User Manual flags of the endpoint that cause the interrupt. This bit will be automatically cleared after the respective endpoint’s flags which cause this interrupt are cleared. Note: Only accessible in device mode. 17:16 Reserved Must be kept at reset value. EOPFIF End of periodic frame interrupt flag When USB bus time in a frame reaches the value defined by EOPFT [1:0] bits in...
Page 901 GD32F20x User Manual Note: Only accessible in host mode. RXFNEIF Rx FIFO non-empty interrupt flag USBFS sets this bit when there is at least one packet or status entry in the Rx FIFO. Note: Accessible in both host and device modes. Start of frame Host Mode: USBFS sets this bit when it prepares to transmit a SOF or Keep-Alive on USB...
Page 902 GD32F20x User Manual Bits Fields Descriptions WKUPIE Wakeup interrupt enable 0: Disable wakeup interrupt 1: Enable wakeup interrupt Note: Accessible in both host and device modes. SESIE Session interrupt enable 0: Disable session interrupt 1: Enable session interrupt Note: Accessible in both host and device modes. DISCIE Disconnect interrupt enable 0: Disable disconnect interrupt...
Page 903 GD32F20x User Manual Note: Only accessible in host mode. 23:22 Reserved Must be kept at reset value. PXNCIE Periodic transfer not complete Interrupt enable 0: Disable periodic transfer not complete interrupt 1: Enable periodic transfer not complete interrupt Note: Only accessible in host mode. ISOONCIE Isochronous OUT transfer not complete interrupt enable 0: Disable isochronous OUT transfer not complete interrupt...
Page 904 GD32F20x User Manual Note: Only accessible in device mode. SPIE USB suspend interrupt enable 0: Disable USB suspend interrupt 1: Enable USB suspend interrupt Note: Only accessible in device mode. ESPIE Early suspend interrupt enable 0: Disable early suspend interrupt 1: Enable early suspend interrupt Note: Only accessible in device mode.
Page 905 GD32F20x User Manual Reserved Must be kept at reset value. Global receive status read/receive status read registers (USBFS_GRSTATR/USBFS_GRSTATP) Address offset for Read: 0x001C Address offset for Pop: 0x0020 Reset value: 0x0000 0000 A read to the receive status read register returns the entry of the top of the Rx FIFO. A read to the Receive status read and pop register additionally pops the top entry out of the Rx FIFO.
Page 906 GD32F20x User Manual 11: MDATA 14:4 BCOUNT[10:0] Byte count The byte count of the received IN data packet. CNUM[3:0] Channel number The channel number to which the current received packet belongs. Device mode: Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:17 RPCKST[3:0] Received packet status...
Page 907 GD32F20x User Manual Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RXFD[15:0] Rx FIFO depth In terms of 32-bit words.
Page 908 GD32F20x User Manual Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host Non-periodic Tx FIFO depth In terms of 32-bit words. 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host Non-periodic Tx FIFO RAM start address The start address for non-periodic Tx FIFO RAM is in term of 32-bit words. Device Mode: Bits Fields...
Page 909 GD32F20x User Manual Bits 30:27: Channel number Bits 26:25: – 00: IN/OUT token – 01: Zero-length OUT packet – 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel. 23:16 NPTXRQS[7:0] Non-periodic Tx request queue space The remaining space of the non-periodic transmit request queue.
Page 910 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. VBUSIG VBUS ignored When this bit is set, USBFS doesn’t monitor the voltage on VBUS pin and always consider V voltage as valid both in host mode and in device mode, then free the V pin for other usage.
Page 911 GD32F20x User Manual Bits Fields Descriptions 31:0 CID[31:0] Core ID Software can write or read this field and uses this field as a unique ID for its application Host periodic Tx FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600 This register has to be accessed by word 32-bit) r/rw r/rw...
Page 912: Host Control And Status Registers
GD32F20x User Manual r/rw r/rw Bits Fields Descriptions 31:16 IEPTXFD[15:0] IN endpoint Tx FIFO depth In terms of 32-bit words. 1≤HPTXFD≤1024 15:0 IEPTXRSAR[15:0] IN endpoint Tx FIFO RAM start address The start address for IN endpoint Tx FIFO is in term of 32-bit words. 28.7.2.
Page 913 GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CLKSEL[1:0] Clock select for USB clock 01: 48MHz clock others: reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the frame interval when USBFS controller is enumerating USB device. This register has to be accessed by word (32-bit) Bits Fields...
Page 914 GD32F20x User Manual Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clocks. 15:0 FRNUM[15:0] Frame number This field reports the frame number of current frame and returns to 0 after it reaches 0x3FFF.
Page 915 GD32F20x User Manual Bits 30:27: Channel Number Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel. 23:16 PTXREQS[7:0] Periodic Tx request queue space The remaining space of the periodic transmit request queue. 0: Request queue is Full 1: 1 entry 2 entries...
Page 916 GD32F20x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. HACHINT[7:0] Host all channel interrupts Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host all channels interrupt enable register (USBFS_HACHINTEN) Address offset: 0x0418 Reset value: 0x0000 0000 This register can be used by software to enable or disable a channel’s interrupt.
Page 917 GD32F20x User Manual rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. 18:17 PS[1:0] Port speed Report the enumerated speed of the device attached to this port. 01: Full speed 10: Low speed Others: Reserved 16:13 Reserved Must be kept at reset value.
Page 918 GD32F20x User Manual – PRST in this register is set – PREM bit in this register is set – A remote wakeup signal is detected – A device disconnect is detected 0: Port is not in suspend state 1: Port is in suspend state PREM Port resume Application sets this bit to start a resume signal on USB port.
Page 919 GD32F20x User Manual EPTYPE[1:0] Bits Fields Descriptions Channel enable Set by the application and cleared by USBFS. 0: Channel disabled 1: Channel enabled Software should following the operation guide to disable or enable a channel. CDIS Channel disable Software can set this bit to disable the channel from processing transactions. Software should follow the operation guide to disable or enable a channel.
Page 920 GD32F20x User Manual The transfer direction of the endpoint that this channel communicates with. 0: OUT 1: IN 14:11 EPNUM[3:0] Endpoint number The number of the endpoint that this channel communicates with. 10:0 MPL[10:0] Maximum packet length The target endpoint’s maximum packet length. Host channel-x interrupt flag register (USBFS_HCHxINTF) (x = 0..7 where x = channel number) Address offset: 0x0508 + (channel_number ×...
Page 921 GD32F20x User Manual maximum packet length. USBER USB Bus Error The USB error flag is set when the following conditions occur during receiving a packet reception: – A received packet has a wrong CRC field – A stuff error detected on USB bus –...
Page 922 GD32F20x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. DTERIE Data toggle error interrupt enable 0: Disable data toggle error interrupt 1: Enable data toggle error interrupt REQOVRIE Request queue overrun interrupt enable 0: Disable request queue overrun interrupt 1: Enable request queue overrun interrupt BBERIE Babble error interrupt enable...
Page 923 GD32F20x User Manual 1: Enable transfer finished interrupt Host channel-x transfer length register (USBFS_HCHxLEN) (x = 0..7, where x = channel number) Address offset: 0x0510 + (channel_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 924: Device Control And Status Registers
GD32F20x User Manual to be transmitted in an OUT transfer. Software should program this field before the channel is enabled. When software successfully writes a packet into the channel’s data Tx FIFO, this field is decreased by the byte size of the packet. For IN transfer each time software or DMA reads out a packet from the RxFIFO, this field is decreased by the byte size of the packet.
Page 925 GD32F20x User Manual Reserved Must be kept at reset value. NZLSOH Non-zero-length status OUT handshake When a USB device receives a non-zero-length data packet during status OUT stage, this field controls that USBFS should either receive this packet or reject this packet with a STALL handshake.
Page 926 GD32F20x User Manual USBFS_GINTF register triggered after a while. Software should clear the GONAK flag before writing this bit again. CGINAK Clear global IN NAK Software sets this bit to clear GINS bit in this register. SGINAK Set global IN NAK Software sets this bit to set GINS bit in this register.
Page 927 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:8 FNRSOF[13:0] The frame number of the received SOF. USBFS always update this field after receiving a SOF token Reserved Must be kept at reset value. ERER Erratic error, set by the core when erratic errors happen.
Page 928 GD32F20x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. IEPNEEN IN endpoint NAK effective interrupt enable bit 0: Disable IN endpoint NAK effective interrupt 1: Enable IN endpoint NAK effective interrupt Reserved Must be kept at reset value. EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 0: Disable endpoint Tx FIFO underrun interrupt...
Page 929 GD32F20x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. BTBSTPEN Back-to-back SETUP packets (only for control OUT endpoint) interrupt enable bit 0: Disable back-to-back SETUP packets interrupt 1: Enable back-to-back SETUP packets interrupt Reserved Must be kept at reset value. EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable bit 0: Disable endpoint Rx FIFO overrun interrupt...
Page 930 GD32F20x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:16 OEPITB[3:0] Device all OUT endpoint interrupt bits Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value...
Page 931 GD32F20x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:16 OEPIE[3:0] Out endpoint interrupt enable 0: Disable OUT endpoint n interrupt 1: Enable OUT endpoint n interrupt Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value.
Page 932 GD32F20x User Manual Device VBUS pulsing time register (USBFS_DVBUSPT) Address offset: 0x082C Reset value: 0x0000 05B8 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DVBUSPT[11:0] Device V pulsing time This field defines the pulsing time for V The true pulsing time is...
Page 933 GD32F20x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. IEPTXFEIE[3:0] IN endpoint Tx FIFO empty interrupt enable bits This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DAEPINT register. Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3 0: Disable FIFO empty interrupt 1: Enable FIFO empty interrupt...
Page 934 GD32F20x User Manual 29:28 Reserved Must be kept at reset value. SNAK Set NAK Software sets this bit to set NAKS bit in this register. CNAK Clear NAK Software sets this bit to clear NAKS bit in this register. 25:22 TXFNUM[3:0] Tx FIFO number Define the Tx FIFO number of IN endpoint 0.
Page 935 GD32F20x User Manual Device IN endpoint-x control register (USBFS_DIEPxCTL) (x = 1..3, where x = endpoint_number) Address offset: 0x0900 + (endpoint_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS.
Page 936 GD32F20x User Manual Software sets this bit to clear NAKS bit in this register. 25:22 TXFNUM[3:0] Tx FIFO number Defines the Tx FIFO number of this IN endpoint. STALL STALL handshake Software can set this bit to send STALL handshake when receiving IN token. This bit has a higher priority than NAKS bit in this register and GINS bit in USBFS_DCTL register.
Page 937 GD32F20x User Manual EPACT Endpoint active This bit controls whether this endpoint is active. If an endpoint is not active, it ignores all tokens and doesn’t make any response. 14:11 Reserved Must be kept at reset value. 10:0 MPL[10:0] This field defines the maximum packet length in byte. Device OUT endpoint 0 control register (USBFS_DOEP0CTL) Address offset: 0x0B00 Reset value: 0x0000 8000...
Page 938 GD32F20x User Manual Set this bit to send STALL handshake during an OUT transaction. USBFS will clear this bit after a SETUP token is received on OUT endpoint 0. This bit has a higher priority than NAKS bit in this register, i.e. if both STALL and NAKS bits are set, the STALL bit takes effect.
Page 939 GD32F20x User Manual rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should follow the operation guide to disable or enable an endpoint.
Page 940 GD32F20x User Manual takes effect. For control OUT endpoint: Only USBFS can clear this bit when a SETUP token is received on the corresponding OUT endpoint. Software is not able to clear it. For interrupt or bulk OUT endpoint: Only software can clear this bit. SNOOP Snoop mode This bit controls the snoop mode of an OUT endpoint.
Page 941 GD32F20x User Manual 14:11 Reserved Must be kept at reset value. 10:0 MPL[10:0] This field defines the maximum packet length in bytes. Device IN endpoint x interrupt flag register (USBFS_DIEPxINTF) (x = 0..3, where x = endpoint_number) Address offset: 0x0908 + (endpoint_number × 0x20) Reset value: 0x0000 0080 This register contains the status and events of an IN endpoint, when an IN endpoint interrupt occurs, read this register for the respective endpoint to get the source of the interrupt.
Page 942 GD32F20x User Manual This flag is triggered if the device waiting for a handshake is timeout in a control IN transaction. Reserved Must be kept at reset value. EPDIS Endpoint disabled This flag is triggered when an endpoint is disabled by the software’s request. Transfer finished This flag is triggered when all the IN transactions assigned to this endpoint have been finished.
Page 943 GD32F20x User Manual data packet and sends a NAK handshake in this case. STPF SETUP phase finished (Only for control OUT endpoint) This flag is triggered when a setup phase finished, i.e. USBFS receives an IN or OUT token after a setup token. Reserved Must be kept at reset value.
Page 944 GD32F20x User Manual the packet. Device OUT endpoint 0 transfer length register (USBFS_DOEP0LEN) Address offset: 0x0B10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions Reserved Must be kept at reset value. 30:29 STPCNT[1:0] SETUP packet count This field defines the maximum number of back-to-back SETUP packets this...
Page 945 GD32F20x User Manual OUT transfer. Program this field before the endpoint is enabled. Each time software reads out a packet from the Rx FIFO, this field is decreased by the byte size of the packet. Device IN endpoint-x transfer length register (USBFS_DIEPxLEN) (x = 1..3, where x = endpoint_number) Address offset: 0x910 + (endpoint_number ×...
Page 946 GD32F20x User Manual Device OUT endpoint-x transfer length register (USBFS_DOEPxLEN) (x = 1..3, where x = endpoint_number) Address offset: 0x0B10 + (endpoint_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions Reserved Must be kept at reset value.
Page 947: Power And Clock Control Register (Usbfs_Pwrclkctl)
GD32F20x User Manual The total data bytes number of a transfer. This field is the total data bytes of all the data packets desired to receive in an OUT transfer. Program this field before the endpoint is enabled. Each time after software reads out a packet from the RxFIFO, this field is decreased by the byte size of the packet.
Page 948 GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SHCLK Stop HCLK Stop the HCLK to save power. 0:HCLK is not stopped 1:HCLK is stopped SUCLK Stop the USB clock Stop the USB clock to save power. 0:USB clock is not stopped 1:USB clock is stopped...
Page 949: Table 29-1. Revision History
GD32F20x User Manual Revision history Table 29-1. Revision history Revision No. Description Date Initial Release Jul.1, 2015 Adapt To New Name Convention Jun.5, 2017 Adapt To New Document Specification Oct 25,2018 Modify the ENET RxDMA descriptor word 0 (RDES0) Bit15 Oct 8,2019...
Page 950 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.