Toshiba GR-200 Series Instruction Manual page 513

Table 4.2-1 Names of operators used in the Interlock-check formulae
Sign of
Interlock
interlock
operator
operator
AND(•)
OR(+)
NOT(!)
COMP
†Note: Q1 and Q2 represent controllable objects.
‡Note: For further information, see Chapter 4.2.3(iii).
Interlock-check method
4.2.3
Node and input/output signals
(i)
A node is represented by an interlock-operator, input signals (stVal and Quality), and output
signals (stVal and Quality). For example, Figure 4.2-3 shows a node with an "OR" interlock-
operator, input signals, and an output signal. When stVal and 'Quality' are applied to the
inputs of the node, the resultant output signal is in accordance with the operation rule of "OR".
(For details, see 4.2.3(iii)-2)
Input(A)
Input(B)
Note: A bold line reflects a signal "stVal". A thin line reflects a signal "Quality". The user
should note that the signal format generated by control functions should be
transposed for the stVal format, as shown in Table 4.2-7.
Description‡
If both input signals are "1", the resultant
output signal is "1". If not, the output signal
is "0".
If either input signals is "1", the resultant
output signal is "1". If not, the output signal
is "0".
If the input signal is "1", the resultant output
signal is "0". If not, the output signal is "1".
Two input signals are compared. If the input
signals are identical, the output signal is "1".
If not, the output signal is "0".
Node
stVal
OR (+)
Quality
stVal
Quality
Figure 4.2-3 Input/output signals
- 494 -
6F2T0200 (0.15)
Example of
interlock
formula†
(Q1) COMP (1)
stVal
Output
Quality
Q1 • Q2
Q1 + Q2
!(Q1)
GRE200 (1,2)