Sanyo FISHER DC-TS960WL Service Manual page 47

IC BLOCK DIAGRAM & DESCRIPTION
IC831,T436416A-SF(DRAM)
CLK 38
22~26,
ADD
29~35
38
CLK
PIN DESCRIPTION
PIN
System Clock
CLK
CS
CKE
A0 ~ A11
Bank Select Address
BA0 ~ BA1
Row Address Strobe
RAS
Column Address Strobe
CAS
WE
Data Input/Output
L(U)DQM
Data Input/Output
DQ0 ~ DQ15
Power Supply/Ground
V ~ V
DD SS
V /V
DDQ SSQ
Power/Ground
Connection/Reserved
N.C/REU
for Future Use
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BA0,BA1
20,21
Bank Select
LRAS LCBR LWE
LCAS
Timing Register
37 19 18
CKE CS RAS
NAME
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enadling all input.
Chip Select
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
Clock Enable CKE shouid be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same oins.
Address
Row address : RA0~RA11,column address : CA0~CA7
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Write Enable
Latches data in starting from CAS,WE active.
Makes data output Hi-Z, t
Mask Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Data Output Isolated power supply and ground for the output buffers to provide improved
noise immunity.
No
This pin is recommended to be left No Connection on the device.
Data Input Register
IM x 16
IM x 16
IM x 16
IM x 16
Column Decode
Latency & Burst Length
LDQM
Programming Register
LWCBR
17 16 15,39
CAS WE L(U)DQM
INPUT FUNCTION
after the clock and masks the output.
SHZ
- 46 -
LWE
15 LDQM
2,4,5,7,8,10,
11,13,42,44,
DQI
45,47,48,50,
51,53