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IC BLOCK DIAGRAM & DESCRIPTION
IC500 M21L216128A-10T(SRAM)
1-5,
18-22,
A0-A16
24-27,
42-44
17-10,
DQ1-DQ8
13-16
CE
6
LB
39
HB
40
OE
41
WE
17
Pin Descriptions
Pin No.
1 - 5, 18 - 22
24 - 27,4 2 - 44
6
7 - 10, 13 - 16
29 - 32, 35 - 38
17
39
40
41
11, 33
12, 34
23, 28
IC900 PQ033ES1MXP(Regulator)
DC INPUT:Vin
3
Control
part
GND
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512 x 4096
Decoder
Input
Column I/O
Data
Circuit
Control
Circuit
Symbol
A0 - A16
CE
DQ1 - DQ16
WE
LB
HB
OE
VCC
GND
NC
1
DC OUTPUT :Vo
2
Memory
Array
Input
Data
Circuit
Description
PAddress Input
Chip Enable Inpu
Data Input / Output
Write Enable Inout
Lower Byte Enable Input (DQ1 to DQ8)
Higher Byte Enable Input (DQ9 to DQ16)
Output Enable Input
Power
Ground
No Connection
- 40 -
11,33
VCC
12,34
GND
29-32,
DQ9-DQ16
35-38
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