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IC BLOCK DIAGRAM & DESCRIPTION
IC560 AK4112BVF(digital Audio Reciver)
RX1
11
RX2
12
Input
Selector
RX3
13
RX4
14
V/TX
4
DVDD
1
DVSS
2
System
Control
PDN
7
No.
Pin Name
1
DVDD
2
DVSS
3
TVDD
V
4
TX
5
XTI
6
XTO
7
PDN
8
R
9
AVDD
10
AVSS
11
RX1
DIF0
12
RX2
DIF1
13
RX3
DIF2
14
RX4
15
AUTO
16
P/S
17
FS96
18
ERF
19
LRCK
20
SDTO
21
BICK
22
DAUX
23
MCK02
24
MCK01
OCKS0
25
CSN
OCKS1
26
CCLK
CM1
27
CDTI
CM0
28
CDTO
NOTE 1 : All input pins except internal pull-down pins should not be left floating
All manuals and user guides at all-guides.com
AUSS AUDD
R
19
9
8
Clock
Recovery
DAIF
Decoder
AC-3/MPEG
Detect
15
AUTO
I/O
-
Digital Power Supply Pin, 3.3V
-
Digitel Ground Pin
-
Input Buffer Power Supply Pin, 3.3V or 5V
O
Validity Flag Output Pin in Parallel Mode
O
Transmit channel (through data) Output Pin in Serial Mode
I
X`tal Input Pin
O
X`tal Output Pin
Power Down Mode Pin
I
When "L", the AK4112B is powered-down and reset
External Resistor Pin
-
18
+/-1% resistor to AVSS externally
-
Analog Power Supply Pin
-
Analog Ground Pin
Receiver Channel 1
I
This channel is selected in Parallel Mode or default of Serial Mode
I
Audio Data Interface Format 0 Pin in Parallel Mode
I
Receiver Channel 2 in Serial Mode
I
Audio Data Interface Format 1 Pin in Parallel Mode
I
Receiver Channel 3 in Secial Mode
I
Audio Data Interface Format 2 Pin in Parallel Mode
I
Receiver Channel 4 in Serial Mode
Non-PCM Detect Pin
O
"L" : No detect, "H" : Detect
Parallel//Serial Select Pin
I
"L" : Serial Mode, "H" : Parallel Mode
96kHz Sampling Detect Pin
O
(RX Mode) "H" : fs=88.2kHz or more. "L" ts=54kHz or less
(X'tal Mode) "H" : XFS96=1, "L" : XFS96=0
Unlock & Parity Error Output Pin
O
"L" : No Error, "H" : Error
I/O
Output Channel Clock Pin
O
Audio Serial Data Output Pin
I/O
Audio Serial Data Clock Pin
I
Auxiliary Audio Data Input Pin
O
Master Clock #2 Output Pin
O
Master Clock #1 Output Pin
I
Output Ciock Select 0 Pin in Parallel Mode
I
Chip Select Pin in Serial Mode
I
Output Clock Select 1 Pin in Parallel Mode
I
Control Data Clock Pin in Serial Mode
I
Master Clock Operation Mode Pin0 in Parallel Mode
I
Control Data Input Pin in Serial Mode
I
Master Clock Operation Mpde Pin1 in Parallel Mode
O
Control Data Output Pin in Serial Mode
MCKO1 MCKO2
XTI
24
23
5
Clock
X'tal
Generator
Oscillator
DEM
Error
Detect
18
ERF
Function
- 42 -
XTO
6
96kHz
17
FS96
Detect
22
DAUX
19
LRCK
Audio
21
BICK
I/F
20
SDTD
3
TVDD
25
CSN
26
CCLK
up I/F
28
CDTO
27
CDTI
16
P/S-"L"
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