Sharp DX-SX1H Service Manual page 63

IC901 VHiCXD2751Q-1: SACD Playback Signal Processor (CXD2751Q) (2/2)
Pin No. Terminal Name Input/Output
46 BCKA
47 DSAL
48 DSAR
49 ZDFLGL
50 ZDFLGR
51 A0
52 A1
53 VDD
54 VSS
55-62 A2-A9
63 A10
64* NC
65 VSS
66 XWE
67 XCAS
68 XRAS
69 XOE
70-77 DQ0-DQ7
78 VDD
79 VSS
80 WCK
81 WRFD
82 WAD0
83-88 WAD1-WAD6
89 WAD7
90 VSS
91 SD7
92-97 SD6-SD1
98 SD0
99 SDEF
100 XSAK
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
SD[7:0]
WAD[7:0]
Input/Output Shift clock input/output terminal for DSD data output. Input/output according to setting.
Output Lch-DSD data output terminal. Phase modulation output according to setting.
Output Rch-DSD data output terminal. Phase modulation output according to setting.
Output Lch zero data detection flag. "H": when silent data continue for 300msec.
Output Rch zero data detection flag. "H": when silent data continue for 300msec.
Output DRAM address output terminal (LSB)
Output DRAM address output terminal
— Power supply terminal, +3.3V
— Ground terminal
Output DRAM address output terminal
Output DRAM address output terminal (MSB)
— Not used
— Ground terminal
Output DRAM write enable output terminal. Connected to WE terminal of DRAM.
Output DRAM column address strobe output terminal. Connected to CAS terminal of DRAM.
Output DRAM row address strobe output terminal. Connected RAS terminal of DRAM.
Output DRAM read enable output terminal. Connected OE terminal of DRAM.
Input/Output DRAM data input/output terminal
— Power supply terminal, +3.3V
— Ground terminal
Input Operation clock for detecting PSP physical disc mark. Inputs 27.00MHz.
Input RF data input terminal for detecting PSP physical disc mark
Inputs RF data made binary by slicer.
Input A/D data input/output terminal for detecting PSP physical disc mark (LSB)
Input A/D data input/output terminal for detecting PSP physical disc mark
Input A/D data input/output terminal for detecting PSP physical disc mark (MSB)
— Ground terminal
Input Input terminal for stream data to be output from the front end processor (MSB)
Input Input terminal for stream data to be output from the front end processor
Input Input terminal for stream data to be output from the front end processor (LSB)
Input Input terminal for error flag to be output from the front end processor
Input Input terminal for data effective flag to be output from the front end processor
63~55,
52, 51
XSRQ 1
SDEF
99
91 ~ 98
SDCK
5
DECRYPTION
XSAK
100
XSHD
2
89 ~ 82
PSP
81
WRFD
WCK 80
11 7
Figure 63 BLOCK DIAGRAM OF IC
Function
68 67 66 69 77 ~ 70
STREAM MANAGER
INPUT/OUTPUT
DIRECT STREAM
TRANSFER DECODER
CPU-I/F
TIMING
8 9 10 13 14 16 17 18 19
– 63 –
SUPDAT
34
XSUPAK
35
SUP-I/F
36 SUPEN
33
F75HZ
FADE-
49
50
BCKA
46
DSD 47 DSAL
I/F
48 DSAR
42 BCKD
6
DX-SX1H